start comments with #
move the constant pool to .text
correctly print loads of labels
mark R0, R1, R2 and R3 as caller save
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@29451 91177308-0d34-0410-b5e6-96231b3b80d8
diff --git a/lib/Target/ARM/ARMAsmPrinter.cpp b/lib/Target/ARM/ARMAsmPrinter.cpp
index 0202832..d998fdf 100644
--- a/lib/Target/ARM/ARMAsmPrinter.cpp
+++ b/lib/Target/ARM/ARMAsmPrinter.cpp
@@ -43,8 +43,8 @@
Data32bitsDirective = "\t.word\t";
Data64bitsDirective = 0;
ZeroDirective = "\t.skip\t";
- CommentString = "!";
- ConstantPoolSection = "\t.section \".rodata\",#alloc\n";
+ CommentString = "#";
+ ConstantPoolSection = "\t.text\n";
AlignmentIsInBytes = false;
}
@@ -60,9 +60,21 @@
}
void printMemRegImm(const MachineInstr *MI, unsigned OpNo) {
- printOperand(MI, OpNo + 1);
- O << ", ";
- printOperand(MI, OpNo);
+ const MachineOperand &MO1 = MI->getOperand(OpNo);
+ const MachineOperand &MO2 = MI->getOperand(OpNo + 1);
+ assert(MO1.isImmediate());
+
+ if (MO2.isConstantPoolIndex()) {
+ printOperand(MI, OpNo + 1);
+ } else if (MO2.isRegister()) {
+ O << '[';
+ printOperand(MI, OpNo + 1);
+ O << ", ";
+ printOperand(MI, OpNo);
+ O << ']';
+ } else {
+ assert(0 && "Invalid Operand Type");
+ }
}
void printOperand(const MachineInstr *MI, int opNum);
diff --git a/lib/Target/ARM/ARMInstrInfo.td b/lib/Target/ARM/ARMInstrInfo.td
index 6c216f2..a749aa0 100644
--- a/lib/Target/ARM/ARMInstrInfo.td
+++ b/lib/Target/ARM/ARMInstrInfo.td
@@ -57,10 +57,12 @@
def bx: InstARM<(ops IntRegs:$dst), "bx $dst", [(brind IntRegs:$dst)]>;
}
-def bl: InstARM<(ops i32imm:$func, variable_ops), "bl $func", [(ARMcall tglobaladdr:$func)]>;
+let Defs = [R0, R1, R2, R3] in {
+ def bl: InstARM<(ops i32imm:$func, variable_ops), "bl $func", [(ARMcall tglobaladdr:$func)]>;
+}
def ldr : InstARM<(ops IntRegs:$dst, memri:$addr),
- "ldr $dst, [$addr]",
+ "ldr $dst, $addr",
[(set IntRegs:$dst, (load iaddr:$addr))]>;
def str : InstARM<(ops IntRegs:$src, IntRegs:$addr),