Make the end-of-itinerary mark explicit. Some cleanup.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@82709 91177308-0d34-0410-b5e6-96231b3b80d8
diff --git a/lib/CodeGen/ExactHazardRecognizer.cpp b/lib/CodeGen/ExactHazardRecognizer.cpp
index 85bf43e..4f32c2b 100644
--- a/lib/CodeGen/ExactHazardRecognizer.cpp
+++ b/lib/CodeGen/ExactHazardRecognizer.cpp
@@ -31,13 +31,11 @@
ScoreboardDepth = 1;
if (!ItinData.isEmpty()) {
for (unsigned idx = 0; ; ++idx) {
- // If the begin stage of an itinerary has 0 cycles and units,
- // then we have reached the end of the itineraries.
- const InstrStage *IS = ItinData.beginStage(idx);
- const InstrStage *E = ItinData.endStage(idx);
- if ((IS->getCycles() == 0) && (IS->getUnits() == 0))
+ if (ItinData.isEndMarker(idx))
break;
+ const InstrStage *IS = ItinData.beginStage(idx);
+ const InstrStage *E = ItinData.endStage(idx);
unsigned ItinDepth = 0;
for (; IS != E; ++IS)
ItinDepth += IS->getCycles();
diff --git a/lib/Target/ARM/ARMSchedule.td b/lib/Target/ARM/ARMSchedule.td
index 1b8fc8b..4dc369a 100644
--- a/lib/Target/ARM/ARMSchedule.td
+++ b/lib/Target/ARM/ARMSchedule.td
@@ -127,90 +127,7 @@
//===----------------------------------------------------------------------===//
// Processor instruction itineraries.
-def GenericItineraries : ProcessorItineraries<[
- InstrItinData<IIC_iALUx , [InstrStage<1, [FU_Pipe0]>]>,
- InstrItinData<IIC_iALUi , [InstrStage<1, [FU_Pipe0]>]>,
- InstrItinData<IIC_iALUr , [InstrStage<1, [FU_Pipe0]>]>,
- InstrItinData<IIC_iALUsi , [InstrStage<1, [FU_Pipe0]>]>,
- InstrItinData<IIC_iALUsr , [InstrStage<1, [FU_Pipe0]>]>,
- InstrItinData<IIC_iUNAr , [InstrStage<1, [FU_Pipe0]>]>,
- InstrItinData<IIC_iUNAsi , [InstrStage<1, [FU_Pipe0]>]>,
- InstrItinData<IIC_iUNAsr , [InstrStage<1, [FU_Pipe0]>]>,
- InstrItinData<IIC_iCMPi , [InstrStage<1, [FU_Pipe0]>]>,
- InstrItinData<IIC_iCMPr , [InstrStage<1, [FU_Pipe0]>]>,
- InstrItinData<IIC_iCMPsi , [InstrStage<1, [FU_Pipe0]>]>,
- InstrItinData<IIC_iCMPsr , [InstrStage<1, [FU_Pipe0]>]>,
- InstrItinData<IIC_iMOVi , [InstrStage<1, [FU_Pipe0]>]>,
- InstrItinData<IIC_iMOVr , [InstrStage<1, [FU_Pipe0]>]>,
- InstrItinData<IIC_iMOVsi , [InstrStage<1, [FU_Pipe0]>]>,
- InstrItinData<IIC_iMOVsr , [InstrStage<1, [FU_Pipe0]>]>,
- InstrItinData<IIC_iCMOVi , [InstrStage<1, [FU_Pipe0]>]>,
- InstrItinData<IIC_iCMOVr , [InstrStage<1, [FU_Pipe0]>]>,
- InstrItinData<IIC_iCMOVsi , [InstrStage<1, [FU_Pipe0]>]>,
- InstrItinData<IIC_iCMOVsr , [InstrStage<1, [FU_Pipe0]>]>,
- InstrItinData<IIC_iMUL16 , [InstrStage<1, [FU_Pipe0]>]>,
- InstrItinData<IIC_iMAC16 , [InstrStage<1, [FU_Pipe0]>]>,
- InstrItinData<IIC_iMUL32 , [InstrStage<1, [FU_Pipe0]>]>,
- InstrItinData<IIC_iMAC32 , [InstrStage<1, [FU_Pipe0]>]>,
- InstrItinData<IIC_iMUL64 , [InstrStage<1, [FU_Pipe0]>]>,
- InstrItinData<IIC_iMAC64 , [InstrStage<1, [FU_Pipe0]>]>,
- InstrItinData<IIC_iLoadi , [InstrStage<1, [FU_Pipe0]>,
- InstrStage<1, [FU_LdSt0]>]>,
- InstrItinData<IIC_iLoadr , [InstrStage<1, [FU_Pipe0]>,
- InstrStage<1, [FU_LdSt0]>]>,
- InstrItinData<IIC_iLoadsi , [InstrStage<1, [FU_Pipe0]>,
- InstrStage<1, [FU_LdSt0]>]>,
- InstrItinData<IIC_iLoadiu , [InstrStage<1, [FU_Pipe0]>,
- InstrStage<1, [FU_LdSt0]>]>,
- InstrItinData<IIC_iLoadru , [InstrStage<1, [FU_Pipe0]>,
- InstrStage<1, [FU_LdSt0]>]>,
- InstrItinData<IIC_iLoadsiu, [InstrStage<1, [FU_Pipe0]>,
- InstrStage<1, [FU_LdSt0]>]>,
- InstrItinData<IIC_iLoadm , [InstrStage<2, [FU_Pipe0]>,
- InstrStage<2, [FU_LdSt0]>]>,
- InstrItinData<IIC_iStorei , [InstrStage<1, [FU_Pipe0]>]>,
- InstrItinData<IIC_iStorer , [InstrStage<1, [FU_Pipe0]>]>,
- InstrItinData<IIC_iStoresi , [InstrStage<1, [FU_Pipe0]>]>,
- InstrItinData<IIC_iStoreiu , [InstrStage<1, [FU_Pipe0]>]>,
- InstrItinData<IIC_iStoreru , [InstrStage<1, [FU_Pipe0]>]>,
- InstrItinData<IIC_iStoresiu, [InstrStage<1, [FU_Pipe0]>]>,
- InstrItinData<IIC_iStorem , [InstrStage<2, [FU_Pipe0]>]>,
- InstrItinData<IIC_Br , [InstrStage<1, [FU_Pipe0]>]>,
- InstrItinData<IIC_fpSTAT , [InstrStage<1, [FU_Pipe0]>]>,
- InstrItinData<IIC_fpMOVSI , [InstrStage<1, [FU_Pipe0]>]>,
- InstrItinData<IIC_fpMOVDI , [InstrStage<1, [FU_Pipe0]>]>,
- InstrItinData<IIC_fpMOVIS , [InstrStage<1, [FU_Pipe0]>]>,
- InstrItinData<IIC_fpMOVID , [InstrStage<1, [FU_Pipe0]>]>,
- InstrItinData<IIC_fpUNA32 , [InstrStage<1, [FU_Pipe0]>]>,
- InstrItinData<IIC_fpUNA64 , [InstrStage<1, [FU_Pipe0]>]>,
- InstrItinData<IIC_fpCMP32 , [InstrStage<1, [FU_Pipe0]>]>,
- InstrItinData<IIC_fpCMP64 , [InstrStage<1, [FU_Pipe0]>]>,
- InstrItinData<IIC_fpCVTSD , [InstrStage<1, [FU_Pipe0]>]>,
- InstrItinData<IIC_fpCVTDS , [InstrStage<1, [FU_Pipe0]>]>,
- InstrItinData<IIC_fpCVTIS , [InstrStage<1, [FU_Pipe0]>]>,
- InstrItinData<IIC_fpCVTID , [InstrStage<1, [FU_Pipe0]>]>,
- InstrItinData<IIC_fpCVTSI , [InstrStage<1, [FU_Pipe0]>]>,
- InstrItinData<IIC_fpCVTDI , [InstrStage<1, [FU_Pipe0]>]>,
- InstrItinData<IIC_fpALU32 , [InstrStage<1, [FU_Pipe0]>]>,
- InstrItinData<IIC_fpALU64 , [InstrStage<1, [FU_Pipe0]>]>,
- InstrItinData<IIC_fpMUL32 , [InstrStage<1, [FU_Pipe0]>]>,
- InstrItinData<IIC_fpMUL64 , [InstrStage<1, [FU_Pipe0]>]>,
- InstrItinData<IIC_fpMAC32 , [InstrStage<1, [FU_Pipe0]>]>,
- InstrItinData<IIC_fpMAC64 , [InstrStage<1, [FU_Pipe0]>]>,
- InstrItinData<IIC_fpDIV32 , [InstrStage<1, [FU_Pipe0]>]>,
- InstrItinData<IIC_fpDIV64 , [InstrStage<1, [FU_Pipe0]>]>,
- InstrItinData<IIC_fpSQRT32 , [InstrStage<1, [FU_Pipe0]>]>,
- InstrItinData<IIC_fpSQRT64 , [InstrStage<1, [FU_Pipe0]>]>,
- InstrItinData<IIC_fpLoad32 , [InstrStage<1, [FU_Pipe0]>,
- InstrStage<1, [FU_LdSt0]>]>,
- InstrItinData<IIC_fpLoad64 , [InstrStage<1, [FU_Pipe0]>,
- InstrStage<1, [FU_LdSt0]>]>,
- InstrItinData<IIC_fpLoadm , [InstrStage<1, [FU_Pipe0]>,
- InstrStage<1, [FU_LdSt0]>]>,
- InstrItinData<IIC_fpStore32, [InstrStage<1, [FU_Pipe0]>]>,
- InstrItinData<IIC_fpStore64, [InstrStage<1, [FU_Pipe0]>]>,
- InstrItinData<IIC_fpStorem , [InstrStage<1, [FU_Pipe0]>]>
-]>;
+def GenericItineraries : ProcessorItineraries<[]>;
include "ARMScheduleV6.td"