commit 2018681e1d5ee5b47cbfeea88bf7f41259069e39
author Evan Cheng <evan.cheng@apple.com> Thu Sep 27 07:35:39 2007 +0000
committer Evan Cheng <evan.cheng@apple.com> Thu Sep 27 07:35:39 2007 +0000
tree e2e851b2fd4dd48b922ef40d4533fece60828017
parent dc07d96051f41a0b30c911e32ff67f8a53a5bdf8

Silence a compiler warning.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@42389 91177308-0d34-0410-b5e6-96231b3b80d8

lib/CodeGen/SelectionDAG/LegalizeDAG.cpp

diff --git a/lib/CodeGen/SelectionDAG/LegalizeDAG.cpp b/lib/CodeGen/SelectionDAG/LegalizeDAG.cpp
index b5c160a..509e225 100644
--- a/lib/CodeGen/SelectionDAG/LegalizeDAG.cpp
+++ b/lib/CodeGen/SelectionDAG/LegalizeDAG.cpp
@@ -5743,7 +5743,7 @@
   case ISD::UINT_TO_FP: {
     bool isSigned = Node->getOpcode() == ISD::SINT_TO_FP;
     MVT::ValueType SrcVT = Node->getOperand(0).getValueType();
-    RTLIB::Libcall LC;
+    RTLIB::Libcall LC = RTLIB::UNKNOWN_LIBCALL;
     if (Node->getOperand(0).getValueType() == MVT::i64) {
       if (VT == MVT::f32)
         LC = isSigned ? RTLIB::SINTTOFP_I64_F32 : RTLIB::UINTTOFP_I64_F32;