commit 2027379985f1cbb965be808adad5b819a66dd97f
author Jakob Stoklund Olesen <stoklund@2pi.dk> Sat Dec 17 00:07:02 2011 +0000
committer Jakob Stoklund Olesen <stoklund@2pi.dk> Sat Dec 17 00:07:02 2011 +0000
tree 1b91f73289af9f20e89e92ec672a3e312bbe7d6f
parent ce16339930a2b03e53b4e6399ef59c092a7f2cfa

Preserve more memory operands in ARMExpandPseudo.

I don't think this affects anything but verbose assembly.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@146787 91177308-0d34-0410-b5e6-96231b3b80d8

lib/Target/ARM/ARMExpandPseudoInsts.cpp

diff --git a/lib/Target/ARM/ARMExpandPseudoInsts.cpp b/lib/Target/ARM/ARMExpandPseudoInsts.cpp
index 01d772d..588570f 100644
--- a/lib/Target/ARM/ARMExpandPseudoInsts.cpp
+++ b/lib/Target/ARM/ARMExpandPseudoInsts.cpp
@@ -631,6 +631,8 @@
     // Add an implicit def for the super-register.
     MIB.addReg(DstReg, RegState::ImplicitDefine | getDeadRegState(DstIsDead));
   TransferImpOps(MI, MIB, MIB);
+  // Transfer memoperands.
+  MIB->setMemRefs(MI.memoperands_begin(), MI.memoperands_end());
   MI.eraseFromParent();
 }
 
@@ -1024,6 +1026,7 @@
       // Add an implicit def for the super-register.
       MIB.addReg(DstReg, RegState::ImplicitDefine | getDeadRegState(DstIsDead));
       TransferImpOps(MI, MIB, MIB);
+      MIB.setMemRefs(MI.memoperands_begin(), MI.memoperands_end());
       MI.eraseFromParent();
       return true;
     }
@@ -1054,6 +1057,7 @@
         MIB->addRegisterKilled(SrcReg, TRI, true);
 
       TransferImpOps(MI, MIB, MIB);
+      MIB.setMemRefs(MI.memoperands_begin(), MI.memoperands_end());
       MI.eraseFromParent();
       return true;
     }