commit 20a20d78ae1fea634b02b2007423ac69b2fbbb52
author Bill Wendling <isanbard@gmail.com> Sat Jan 05 23:30:51 2008 +0000
committer Bill Wendling <isanbard@gmail.com> Sat Jan 05 23:30:51 2008 +0000
tree 5c42a43d1a0e18c49921550093a4ad1eac19d406
parent e2f2c4cf6fdfbaf99c53bb8de4c3d53466e4ba52

Fix comment.


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@45638 91177308-0d34-0410-b5e6-96231b3b80d8

lib/Target/X86/X86InstrInfo.cpp

diff --git a/lib/Target/X86/X86InstrInfo.cpp b/lib/Target/X86/X86InstrInfo.cpp
index 9d71427..c19827e 100644
--- a/lib/Target/X86/X86InstrInfo.cpp
+++ b/lib/Target/X86/X86InstrInfo.cpp
@@ -173,8 +173,7 @@
       unsigned Reg = MI->getOperand(1).getReg();
       const X86Subtarget &ST = TM.getSubtarget<X86Subtarget>();
 
-      // Loads from global addresses which aren't redefined in the function are
-      // side effect free.
+      // Loads from stubs of global addresses are side effect free.
       if (Reg != 0 && MRegisterInfo::isVirtualRegister(Reg) &&
           MI->getOperand(2).isImm() && MI->getOperand(3).isReg() &&
           MI->getOperand(4).isGlobal() &&