MIPS DSP: add operands to make sure instruction strings are being matched.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@164849 91177308-0d34-0410-b5e6-96231b3b80d8
diff --git a/test/CodeGen/Mips/dsp-r2.ll b/test/CodeGen/Mips/dsp-r2.ll
index 4656f70..631f9e4 100644
--- a/test/CodeGen/Mips/dsp-r2.ll
+++ b/test/CodeGen/Mips/dsp-r2.ll
@@ -539,7 +539,7 @@
define i32 @test__builtin_mips_append1(i32 %i0, i32 %a0, i32 %a1) nounwind readnone {
entry:
-; CHECK: append
+; CHECK: append ${{[0-9]+}}
%0 = tail call i32 @llvm.mips.append(i32 %a0, i32 %a1, i32 15)
ret i32 %0
@@ -549,7 +549,7 @@
define i32 @test__builtin_mips_balign1(i32 %i0, i32 %a0, i32 %a1) nounwind readnone {
entry:
-; CHECK: balign
+; CHECK: balign ${{[0-9]+}}
%0 = tail call i32 @llvm.mips.balign(i32 %a0, i32 %a1, i32 1)
ret i32 %0
@@ -559,7 +559,7 @@
define i32 @test__builtin_mips_prepend1(i32 %i0, i32 %a0, i32 %a1) nounwind readnone {
entry:
-; CHECK: prepend
+; CHECK: prepend ${{[0-9]+}}
%0 = tail call i32 @llvm.mips.prepend(i32 %a0, i32 %a1, i32 15)
ret i32 %0