Add support for 64-bit arguments
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@24792 91177308-0d34-0410-b5e6-96231b3b80d8
diff --git a/lib/Target/Sparc/SparcISelDAGToDAG.cpp b/lib/Target/Sparc/SparcISelDAGToDAG.cpp
index a2eb9c7..a17637a 100644
--- a/lib/Target/Sparc/SparcISelDAGToDAG.cpp
+++ b/lib/Target/Sparc/SparcISelDAGToDAG.cpp
@@ -102,6 +102,18 @@
Arg = DAG.getNode(ISD::TRUNCATE, ObjectVT, Arg);
}
ArgValues.push_back(Arg);
+ break;
+ }
+ case MVT::i64: {
+ unsigned VRegLo = RegMap->createVirtualRegister(&V8::IntRegsRegClass);
+ MF.addLiveIn(GPR[ArgNo++], VRegLo);
+ unsigned VRegHi = RegMap->createVirtualRegister(&V8::IntRegsRegClass);
+ MF.addLiveIn(GPR[ArgNo++], VRegHi);
+ SDOperand ArgLo = DAG.getCopyFromReg(DAG.getRoot(), VRegLo, MVT::i32);
+ SDOperand ArgHi = DAG.getCopyFromReg(ArgLo.getValue(1), VRegHi, MVT::i32);
+ DAG.setRoot(ArgHi.getValue(1));
+ ArgValues.push_back(DAG.getNode(ISD::BUILD_PAIR, MVT::i64, ArgLo, ArgHi));
+ break;
}
}
}