commit 21f587ca243c2265e9b8aa81481f9085cd0e7b68
author Jim Laskey <jlaskey@mac.com> Tue Oct 18 16:59:23 2005 +0000
committer Jim Laskey <jlaskey@mac.com> Tue Oct 18 16:59:23 2005 +0000
tree 2e87c7853df6c10c8f1677d446f84981b4b7d8d6
parent 841d12d9ac489ec33d933af96d77dd4fc2a4cee2

Simple edits; remove unimplimented cases and clarify long haul SLU cases.


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@23788 91177308-0d34-0410-b5e6-96231b3b80d8

lib/Target/PowerPC/PPCScheduleG5.td

diff --git a/lib/Target/PowerPC/PPCScheduleG5.td b/lib/Target/PowerPC/PPCScheduleG5.td
index 33fe71d..4738b89 100644
--- a/lib/Target/PowerPC/PPCScheduleG5.td
+++ b/lib/Target/PowerPC/PPCScheduleG5.td
@@ -19,7 +19,6 @@
   InstrItinData<IntMFFS     , [InstrStage<6, [IU2]>]>,
   InstrItinData<IntMFVSCR   , [InstrStage<1, [VFPU]>]>,
   InstrItinData<IntMTFSB0   , [InstrStage<6, [FPU1, FPU2]>]>,
-  InstrItinData<IntMTSRD    , [InstrStage<0, [NoUnit]>]>,
   InstrItinData<IntMulHD    , [InstrStage<7, [IU1, IU2]>]>,
   InstrItinData<IntMulHW    , [InstrStage<5, [IU1, IU2]>]>,
   InstrItinData<IntMulHWU   , [InstrStage<5, [IU1, IU2]>]>,
@@ -34,12 +33,10 @@
   InstrItinData<BrCR        , [InstrStage<4, [BPU]>]>,
   InstrItinData<BrMCR       , [InstrStage<2, [BPU]>]>,
   InstrItinData<BrMCRX      , [InstrStage<3, [BPU]>]>,
-  InstrItinData<LdStDCBA    , [InstrStage<0, [NoUnit]>]>,
   InstrItinData<LdStDCBF    , [InstrStage<3, [SLU]>]>,
-  InstrItinData<LdStDCBI    , [InstrStage<0, [NoUnit]>]>,
   InstrItinData<LdStDCBT    , [InstrStage<3, [SLU]>]>,
   InstrItinData<LdStDSS     , [InstrStage<10, [SLU]>]>,
-  InstrItinData<LdStICBI    , [InstrStage<0, [SLU]>]>,
+  InstrItinData<LdStICBI    , [InstrStage<40, [SLU]>]>,
   InstrItinData<LdStLBZUX   , [InstrStage<4, [SLU]>]>,
   InstrItinData<LdStLD      , [InstrStage<3, [SLU]>]>,
   InstrItinData<LdStLDARX   , [InstrStage<11, [SLU]>]>,
@@ -50,14 +47,14 @@
   InstrItinData<LdStLVEBX   , [InstrStage<3, [SLU]>]>,
   InstrItinData<LdStLWA     , [InstrStage<5, [SLU]>]>,
   InstrItinData<LdStLWARX   , [InstrStage<11, [SLU]>]>,
-  InstrItinData<LdStSLBIA   , [InstrStage<0, [SLU]>]>,
+  InstrItinData<LdStSLBIA   , [InstrStage<40, [SLU]>]>, // needs work
   InstrItinData<LdStSLBIE   , [InstrStage<2, [SLU]>]>,
   InstrItinData<LdStSTD     , [InstrStage<3, [SLU]>]>,
   InstrItinData<LdStSTDCX   , [InstrStage<11, [SLU]>]>,
   InstrItinData<LdStSTVEBX  , [InstrStage<5, [SLU]>]>,
   InstrItinData<LdStSTWCX   , [InstrStage<11, [SLU]>]>,
   InstrItinData<LdStSync    , [InstrStage<35, [SLU]>]>,
-  InstrItinData<SprISYNC    , [InstrStage<0, [SLU]>]>,
+  InstrItinData<SprISYNC    , [InstrStage<40, [SLU]>]>, // needs work
   InstrItinData<SprMFSR     , [InstrStage<3, [SLU]>]>,
   InstrItinData<SprMTMSR    , [InstrStage<3, [SLU]>]>,
   InstrItinData<SprMTSR     , [InstrStage<3, [SLU]>]>,
@@ -67,8 +64,6 @@
   InstrItinData<SprMFSPR    , [InstrStage<3, [IU2]>]>,
   InstrItinData<SprMFTB     , [InstrStage<10, [IU2]>]>,
   InstrItinData<SprMTSPR    , [InstrStage<8, [IU2]>]>,
-  InstrItinData<SprMTSRIN   , [InstrStage<0, [NoUnit]>]>,
-  InstrItinData<SprRFI      , [InstrStage<0, [NoUnit]>]>,
   InstrItinData<SprSC       , [InstrStage<1, [IU2]>]>,
   InstrItinData<FPGeneral   , [InstrStage<6, [FPU1, FPU2]>]>,
   InstrItinData<FPCompare   , [InstrStage<8, [FPU1, FPU2]>]>,