commit 221a4371f95ebdb25ac7d4363accb35c88cb5ea4
author Dan Gohman <gohman@apple.com> Mon Jul 07 23:14:23 2008 +0000
committer Dan Gohman <gohman@apple.com> Mon Jul 07 23:14:23 2008 +0000
tree 24fe54b796f3f450ba6aff12b7357068ca66e341
parent ed825d11548be9f8268490d26d0d0bab0347d6fd

Pool-allocation for MachineInstrs, MachineBasicBlocks, and
MachineMemOperands. The pools are owned by MachineFunctions.

This drastically reduces the number of calls to malloc/free made
during the "Emit" phase of scheduling, as well as later phases
in CodeGen. Combined with other changes, this speeds up the
"instruction selection" phase of CodeGen by 10% in some cases.


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@53212 91177308-0d34-0410-b5e6-96231b3b80d8

lib/Target/Alpha/AlphaISelLowering.cpp

diff --git a/lib/Target/Alpha/AlphaISelLowering.cpp b/lib/Target/Alpha/AlphaISelLowering.cpp
index bf3a31d..0f7fd80 100644
--- a/lib/Target/Alpha/AlphaISelLowering.cpp
+++ b/lib/Target/Alpha/AlphaISelLowering.cpp
@@ -662,18 +662,18 @@
   //test sc and maybe branck to start
   //exit:
   const BasicBlock *LLVM_BB = BB->getBasicBlock();
-  ilist<MachineBasicBlock>::iterator It = BB;
+  MachineFunction::iterator It = BB;
   ++It;
   
   MachineBasicBlock *thisMBB = BB;
-  MachineBasicBlock *llscMBB = new MachineBasicBlock(LLVM_BB);
-  MachineBasicBlock *sinkMBB = new MachineBasicBlock(LLVM_BB);
+  MachineFunction *F = BB->getParent();
+  MachineBasicBlock *llscMBB = F->CreateMachineBasicBlock(LLVM_BB);
+  MachineBasicBlock *sinkMBB = F->CreateMachineBasicBlock(LLVM_BB);
 
   sinkMBB->transferSuccessors(thisMBB);
 
-  MachineFunction *F = BB->getParent();
-  F->getBasicBlockList().insert(It, llscMBB);
-  F->getBasicBlockList().insert(It, sinkMBB);
+  F->insert(It, llscMBB);
+  F->insert(It, sinkMBB);
 
   BuildMI(thisMBB, TII->get(Alpha::BR)).addMBB(llscMBB);
   
@@ -719,7 +719,7 @@
   thisMBB->addSuccessor(llscMBB);
   llscMBB->addSuccessor(llscMBB);
   llscMBB->addSuccessor(sinkMBB);
-  delete MI;   // The pseudo instruction is gone now.
+  F->DeleteMachineInstr(MI);   // The pseudo instruction is gone now.
 
   return sinkMBB;
 }

lib/Target/Alpha/AlphaInstrInfo.cpp

diff --git a/lib/Target/Alpha/AlphaInstrInfo.cpp b/lib/Target/Alpha/AlphaInstrInfo.cpp
index 6f96ff0..a602770 100644
--- a/lib/Target/Alpha/AlphaInstrInfo.cpp
+++ b/lib/Target/Alpha/AlphaInstrInfo.cpp
@@ -194,7 +194,7 @@
   else
     abort();
   MachineInstrBuilder MIB = 
-    BuildMI(get(Opc)).addReg(SrcReg, false, false, isKill);
+    BuildMI(MF, get(Opc)).addReg(SrcReg, false, false, isKill);
   for (unsigned i = 0, e = Addr.size(); i != e; ++i) {
     MachineOperand &MO = Addr[i];
     if (MO.isRegister())
@@ -239,7 +239,7 @@
   else
     abort();
   MachineInstrBuilder MIB = 
-    BuildMI(get(Opc), DestReg);
+    BuildMI(MF, get(Opc), DestReg);
   for (unsigned i = 0, e = Addr.size(); i != e; ++i) {
     MachineOperand &MO = Addr[i];
     if (MO.isRegister())
@@ -272,7 +272,7 @@
          bool isKill = MI->getOperand(1).isKill();
          Opc = (Opc == Alpha::BISr) ? Alpha::STQ : 
            ((Opc == Alpha::CPYSS) ? Alpha::STS : Alpha::STT);
-         NewMI = BuildMI(get(Opc)).addReg(InReg, false, false, isKill)
+         NewMI = BuildMI(MF, get(Opc)).addReg(InReg, false, false, isKill)
            .addFrameIndex(FrameIndex)
            .addReg(Alpha::F31);
        } else {           // load -> move
@@ -280,7 +280,7 @@
          bool isDead = MI->getOperand(0).isDead();
          Opc = (Opc == Alpha::BISr) ? Alpha::LDQ : 
            ((Opc == Alpha::CPYSS) ? Alpha::LDS : Alpha::LDT);
-         NewMI = BuildMI(get(Opc)).addReg(OutReg, true, false, false, isDead)
+         NewMI = BuildMI(MF, get(Opc)).addReg(OutReg, true, false, false, isDead)
            .addFrameIndex(FrameIndex)
            .addReg(Alpha::F31);
        }

lib/Target/Alpha/AlphaRegisterInfo.cpp

diff --git a/lib/Target/Alpha/AlphaRegisterInfo.cpp b/lib/Target/Alpha/AlphaRegisterInfo.cpp
index e0859b5..dd8460a 100644
--- a/lib/Target/Alpha/AlphaRegisterInfo.cpp
+++ b/lib/Target/Alpha/AlphaRegisterInfo.cpp
@@ -103,7 +103,7 @@
 // if frame pointer elimination is disabled.
 //
 bool AlphaRegisterInfo::hasFP(const MachineFunction &MF) const {
-  MachineFrameInfo *MFI = MF.getFrameInfo();
+  const MachineFrameInfo *MFI = MF.getFrameInfo();
   return MFI->hasVarSizedObjects();
 }
 
@@ -125,11 +125,11 @@
 
       MachineInstr *New;
       if (Old->getOpcode() == Alpha::ADJUSTSTACKDOWN) {
-        New=BuildMI(TII.get(Alpha::LDA), Alpha::R30)
+        New=BuildMI(MF, TII.get(Alpha::LDA), Alpha::R30)
           .addImm(-Amount).addReg(Alpha::R30);
       } else {
          assert(Old->getOpcode() == Alpha::ADJUSTSTACKUP);
-         New=BuildMI(TII.get(Alpha::LDA), Alpha::R30)
+         New=BuildMI(MF, TII.get(Alpha::LDA), Alpha::R30)
           .addImm(Amount).addReg(Alpha::R30);
       }
 
@@ -188,7 +188,7 @@
     MI.getOperand(i + 1).ChangeToRegister(Alpha::R28, false);
     MI.getOperand(i).ChangeToImmediate(getLower16(Offset));
     //insert the new
-    MachineInstr* nMI=BuildMI(TII.get(Alpha::LDAH), Alpha::R28)
+    MachineInstr* nMI=BuildMI(MF, TII.get(Alpha::LDAH), Alpha::R28)
       .addImm(getUpper16(Offset)).addReg(FP ? Alpha::R15 : Alpha::R30);
     MBB.insert(II, nMI);
   } else {