commit 221a4371f95ebdb25ac7d4363accb35c88cb5ea4
author Dan Gohman <gohman@apple.com> Mon Jul 07 23:14:23 2008 +0000
committer Dan Gohman <gohman@apple.com> Mon Jul 07 23:14:23 2008 +0000
tree 24fe54b796f3f450ba6aff12b7357068ca66e341
parent ed825d11548be9f8268490d26d0d0bab0347d6fd

Pool-allocation for MachineInstrs, MachineBasicBlocks, and
MachineMemOperands. The pools are owned by MachineFunctions.

This drastically reduces the number of calls to malloc/free made
during the "Emit" phase of scheduling, as well as later phases
in CodeGen. Combined with other changes, this speeds up the
"instruction selection" phase of CodeGen by 10% in some cases.


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@53212 91177308-0d34-0410-b5e6-96231b3b80d8

lib/Target/Sparc/SparcInstrInfo.cpp

diff --git a/lib/Target/Sparc/SparcInstrInfo.cpp b/lib/Target/Sparc/SparcInstrInfo.cpp
index 67df87b..2476f4c 100644
--- a/lib/Target/Sparc/SparcInstrInfo.cpp
+++ b/lib/Target/Sparc/SparcInstrInfo.cpp
@@ -162,7 +162,7 @@
     Opc = SP::STDFri;
   else
     assert(0 && "Can't load this register");
-  MachineInstrBuilder MIB = BuildMI(get(Opc));
+  MachineInstrBuilder MIB = BuildMI(MF, get(Opc));
   for (unsigned i = 0, e = Addr.size(); i != e; ++i) {
     MachineOperand &MO = Addr[i];
     if (MO.isRegister())
@@ -206,7 +206,7 @@
     Opc = SP::LDDFri;
   else
     assert(0 && "Can't load this register");
-  MachineInstrBuilder MIB = BuildMI(get(Opc), DestReg);
+  MachineInstrBuilder MIB = BuildMI(MF, get(Opc), DestReg);
   for (unsigned i = 0, e = Addr.size(); i != e; ++i) {
     MachineOperand &MO = Addr[i];
     if (MO.isReg())
@@ -236,10 +236,10 @@
     if (MI->getOperand(1).isRegister() && MI->getOperand(1).getReg() == SP::G0&&
         MI->getOperand(0).isRegister() && MI->getOperand(2).isRegister()) {
       if (OpNum == 0)    // COPY -> STORE
-        NewMI = BuildMI(get(SP::STri)).addFrameIndex(FI).addImm(0)
+        NewMI = BuildMI(MF, get(SP::STri)).addFrameIndex(FI).addImm(0)
                                    .addReg(MI->getOperand(2).getReg());
       else               // COPY -> LOAD
-        NewMI = BuildMI(get(SP::LDri), MI->getOperand(0).getReg())
+        NewMI = BuildMI(MF, get(SP::LDri), MI->getOperand(0).getReg())
                       .addFrameIndex(FI).addImm(0);
     }
     break;
@@ -250,12 +250,12 @@
     if (OpNum == 0) { // COPY -> STORE
       unsigned SrcReg = MI->getOperand(1).getReg();
       bool isKill = MI->getOperand(1).isKill();
-      NewMI = BuildMI(get(isFloat ? SP::STFri : SP::STDFri))
+      NewMI = BuildMI(MF, get(isFloat ? SP::STFri : SP::STDFri))
         .addFrameIndex(FI).addImm(0).addReg(SrcReg, false, false, isKill);
     } else {             // COPY -> LOAD
       unsigned DstReg = MI->getOperand(0).getReg();
       bool isDead = MI->getOperand(0).isDead();
-      NewMI = BuildMI(get(isFloat ? SP::LDFri : SP::LDDFri))
+      NewMI = BuildMI(MF, get(isFloat ? SP::LDFri : SP::LDDFri))
         .addReg(DstReg, true, false, false, isDead).addFrameIndex(FI).addImm(0);
     }
     break;