commit 226036ee731a2041f37f28f958d2b6a50373f4f4
author Bob Wilson <bob.wilson@apple.com> Sat Mar 20 22:13:40 2010 +0000
committer Bob Wilson <bob.wilson@apple.com> Sat Mar 20 22:13:40 2010 +0000
tree 810462699200a53793f916326b5e6f9726aeaa31
parent d5fadaf56ee1e8ee137d34bed6749bd3b11ffd88

Re-commit r98683 ("remove redundant writeback flag from ARM address mode 6")
with changes to add a separate optional register update argument.  Change all
the NEON instructions with address register writeback to use it.


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@99095 91177308-0d34-0410-b5e6-96231b3b80d8

lib/Target/ARM/NEONPreAllocPass.cpp

diff --git a/lib/Target/ARM/NEONPreAllocPass.cpp b/lib/Target/ARM/NEONPreAllocPass.cpp
index b010c5a..c36fe63 100644
--- a/lib/Target/ARM/NEONPreAllocPass.cpp
+++ b/lib/Target/ARM/NEONPreAllocPass.cpp
@@ -177,20 +177,20 @@
   case ARM::VST2LNd8:
   case ARM::VST2LNd16:
   case ARM::VST2LNd32:
-    FirstOpnd = 4;
+    FirstOpnd = 2;
     NumRegs = 2;
     return true;
 
   case ARM::VST2q8:
   case ARM::VST2q16:
   case ARM::VST2q32:
-    FirstOpnd = 4;
+    FirstOpnd = 2;
     NumRegs = 4;
     return true;
 
   case ARM::VST2LNq16:
   case ARM::VST2LNq32:
-    FirstOpnd = 4;
+    FirstOpnd = 2;
     NumRegs = 2;
     Offset = 0;
     Stride = 2;
@@ -198,7 +198,7 @@
 
   case ARM::VST2LNq16odd:
   case ARM::VST2LNq32odd:
-    FirstOpnd = 4;
+    FirstOpnd = 2;
     NumRegs = 2;
     Offset = 1;
     Stride = 2;
@@ -211,14 +211,14 @@
   case ARM::VST3LNd8:
   case ARM::VST3LNd16:
   case ARM::VST3LNd32:
-    FirstOpnd = 4;
+    FirstOpnd = 2;
     NumRegs = 3;
     return true;
 
   case ARM::VST3q8_UPD:
   case ARM::VST3q16_UPD:
   case ARM::VST3q32_UPD:
-    FirstOpnd = 5;
+    FirstOpnd = 4;
     NumRegs = 3;
     Offset = 0;
     Stride = 2;
@@ -227,7 +227,7 @@
   case ARM::VST3q8odd_UPD:
   case ARM::VST3q16odd_UPD:
   case ARM::VST3q32odd_UPD:
-    FirstOpnd = 5;
+    FirstOpnd = 4;
     NumRegs = 3;
     Offset = 1;
     Stride = 2;
@@ -235,7 +235,7 @@
 
   case ARM::VST3LNq16:
   case ARM::VST3LNq32:
-    FirstOpnd = 4;
+    FirstOpnd = 2;
     NumRegs = 3;
     Offset = 0;
     Stride = 2;
@@ -243,7 +243,7 @@
 
   case ARM::VST3LNq16odd:
   case ARM::VST3LNq32odd:
-    FirstOpnd = 4;
+    FirstOpnd = 2;
     NumRegs = 3;
     Offset = 1;
     Stride = 2;
@@ -256,14 +256,14 @@
   case ARM::VST4LNd8:
   case ARM::VST4LNd16:
   case ARM::VST4LNd32:
-    FirstOpnd = 4;
+    FirstOpnd = 2;
     NumRegs = 4;
     return true;
 
   case ARM::VST4q8_UPD:
   case ARM::VST4q16_UPD:
   case ARM::VST4q32_UPD:
-    FirstOpnd = 5;
+    FirstOpnd = 4;
     NumRegs = 4;
     Offset = 0;
     Stride = 2;
@@ -272,7 +272,7 @@
   case ARM::VST4q8odd_UPD:
   case ARM::VST4q16odd_UPD:
   case ARM::VST4q32odd_UPD:
-    FirstOpnd = 5;
+    FirstOpnd = 4;
     NumRegs = 4;
     Offset = 1;
     Stride = 2;
@@ -280,7 +280,7 @@
 
   case ARM::VST4LNq16:
   case ARM::VST4LNq32:
-    FirstOpnd = 4;
+    FirstOpnd = 2;
     NumRegs = 4;
     Offset = 0;
     Stride = 2;
@@ -288,7 +288,7 @@
 
   case ARM::VST4LNq16odd:
   case ARM::VST4LNq32odd:
-    FirstOpnd = 4;
+    FirstOpnd = 2;
     NumRegs = 4;
     Offset = 1;
     Stride = 2;