Merge XXXGenRegisterNames.inc into XXXGenRegisterInfo.inc
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@134024 91177308-0d34-0410-b5e6-96231b3b80d8
diff --git a/utils/TableGen/InstrInfoEmitter.cpp b/utils/TableGen/InstrInfoEmitter.cpp
index fa2b192..2f21ea6 100644
--- a/utils/TableGen/InstrInfoEmitter.cpp
+++ b/utils/TableGen/InstrInfoEmitter.cpp
@@ -156,9 +156,15 @@
// run - Emit the main instruction description records for the target...
void InstrInfoEmitter::run(raw_ostream &OS) {
+ emitEnums(OS);
+
GatherItinClasses();
EmitSourceFileHeader("Target Instruction Descriptors", OS);
+
+ OS << "\n#ifdef GET_INSTRINFO_MC_DESC\n";
+ OS << "#undef GET_INSTRINFO_MC_DESC\n";
+
OS << "namespace llvm {\n\n";
CodeGenTarget &Target = CDP.getTargetInfo();
@@ -202,6 +208,8 @@
OperandInfoIDs, OS);
OS << "};\n";
OS << "} // End llvm namespace \n";
+
+ OS << "#endif // GET_INSTRINFO_MC_DESC\n\n";
}
void InstrInfoEmitter::emitRecord(const CodeGenInstruction &Inst, unsigned Num,
@@ -283,3 +291,38 @@
OS << " }, // Inst #" << Num << " = " << Inst.TheDef->getName() << "\n";
}
+
+// emitEnums - Print out enum values for all of the instructions.
+void InstrInfoEmitter::emitEnums(raw_ostream &OS) {
+ EmitSourceFileHeader("Target Instruction Enum Values", OS);
+
+ OS << "\n#ifdef GET_INSTRINFO_ENUM\n";
+ OS << "#undef GET_INSTRINFO_ENUM\n";
+
+ OS << "namespace llvm {\n\n";
+
+ CodeGenTarget Target(Records);
+
+ // We must emit the PHI opcode first...
+ std::string Namespace = Target.getInstNamespace();
+
+ if (Namespace.empty()) {
+ fprintf(stderr, "No instructions defined!\n");
+ exit(1);
+ }
+
+ const std::vector<const CodeGenInstruction*> &NumberedInstructions =
+ Target.getInstructionsByEnumValue();
+
+ OS << "namespace " << Namespace << " {\n";
+ OS << " enum {\n";
+ for (unsigned i = 0, e = NumberedInstructions.size(); i != e; ++i) {
+ OS << " " << NumberedInstructions[i]->TheDef->getName()
+ << "\t= " << i << ",\n";
+ }
+ OS << " INSTRUCTION_LIST_END = " << NumberedInstructions.size() << "\n";
+ OS << " };\n}\n";
+ OS << "} // End llvm namespace \n";
+
+ OS << "#endif // GET_INSTRINFO_ENUM\n\n";
+}
diff --git a/utils/TableGen/InstrInfoEmitter.h b/utils/TableGen/InstrInfoEmitter.h
index a665d40..165ce42 100644
--- a/utils/TableGen/InstrInfoEmitter.h
+++ b/utils/TableGen/InstrInfoEmitter.h
@@ -39,8 +39,9 @@
void run(raw_ostream &OS);
private:
- typedef std::map<std::vector<std::string>, unsigned> OperandInfoMapTy;
-
+ void emitEnums(raw_ostream &OS);
+
+ typedef std::map<std::vector<std::string>, unsigned> OperandInfoMapTy;
void emitRecord(const CodeGenInstruction &Inst, unsigned Num,
Record *InstrInfo,
std::map<std::vector<Record*>, unsigned> &EL,
diff --git a/utils/TableGen/TableGen.cpp b/utils/TableGen/TableGen.cpp
index 6f220c9..ce16c9a 100644
--- a/utils/TableGen/TableGen.cpp
+++ b/utils/TableGen/TableGen.cpp
@@ -28,7 +28,6 @@
#include "EDEmitter.h"
#include "Error.h"
#include "FastISelEmitter.h"
-#include "InstrEnumEmitter.h"
#include "InstrInfoEmitter.h"
#include "IntrinsicEmitter.h"
#include "LLVMCConfigurationEmitter.h"
@@ -55,7 +54,9 @@
PrintRecords,
GenEmitter,
GenRegisterInfo,
- GenInstrEnums, GenInstrs, GenAsmWriter, GenAsmMatcher,
+ GenInstrInfo,
+ GenAsmWriter,
+ GenAsmMatcher,
GenARMDecoder,
GenDisassembler,
GenCallingConv,
@@ -95,9 +96,7 @@
"Generate machine code emitter"),
clEnumValN(GenRegisterInfo, "gen-register-info",
"Generate registers and register classes info"),
- clEnumValN(GenInstrEnums, "gen-instr-enums",
- "Generate enum values for instructions"),
- clEnumValN(GenInstrs, "gen-instr-desc",
+ clEnumValN(GenInstrInfo, "gen-instr-info",
"Generate instruction descriptions"),
clEnumValN(GenCallingConv, "gen-callingconv",
"Generate calling convention descriptions"),
@@ -260,10 +259,7 @@
case GenRegisterInfo:
RegisterInfoEmitter(Records).run(Out.os());
break;
- case GenInstrEnums:
- InstrEnumEmitter(Records).run(Out.os());
- break;
- case GenInstrs:
+ case GenInstrInfo:
InstrInfoEmitter(Records).run(Out.os());
break;
case GenCallingConv: