Merge XXXGenRegisterNames.inc into XXXGenRegisterInfo.inc
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@134024 91177308-0d34-0410-b5e6-96231b3b80d8
diff --git a/utils/TableGen/TableGen.cpp b/utils/TableGen/TableGen.cpp
index 6f220c9..ce16c9a 100644
--- a/utils/TableGen/TableGen.cpp
+++ b/utils/TableGen/TableGen.cpp
@@ -28,7 +28,6 @@
#include "EDEmitter.h"
#include "Error.h"
#include "FastISelEmitter.h"
-#include "InstrEnumEmitter.h"
#include "InstrInfoEmitter.h"
#include "IntrinsicEmitter.h"
#include "LLVMCConfigurationEmitter.h"
@@ -55,7 +54,9 @@
PrintRecords,
GenEmitter,
GenRegisterInfo,
- GenInstrEnums, GenInstrs, GenAsmWriter, GenAsmMatcher,
+ GenInstrInfo,
+ GenAsmWriter,
+ GenAsmMatcher,
GenARMDecoder,
GenDisassembler,
GenCallingConv,
@@ -95,9 +96,7 @@
"Generate machine code emitter"),
clEnumValN(GenRegisterInfo, "gen-register-info",
"Generate registers and register classes info"),
- clEnumValN(GenInstrEnums, "gen-instr-enums",
- "Generate enum values for instructions"),
- clEnumValN(GenInstrs, "gen-instr-desc",
+ clEnumValN(GenInstrInfo, "gen-instr-info",
"Generate instruction descriptions"),
clEnumValN(GenCallingConv, "gen-callingconv",
"Generate calling convention descriptions"),
@@ -260,10 +259,7 @@
case GenRegisterInfo:
RegisterInfoEmitter(Records).run(Out.os());
break;
- case GenInstrEnums:
- InstrEnumEmitter(Records).run(Out.os());
- break;
- case GenInstrs:
+ case GenInstrInfo:
InstrInfoEmitter(Records).run(Out.os());
break;
case GenCallingConv: