| //===- ARMInstrInfo.cpp - ARM Instruction Information -----------*- C++ -*-===// |
| // |
| // The LLVM Compiler Infrastructure |
| // |
| // This file is distributed under the University of Illinois Open Source |
| // License. See LICENSE.TXT for details. |
| // |
| //===----------------------------------------------------------------------===// |
| // |
| // This file contains the ARM implementation of the TargetInstrInfo class. |
| // |
| //===----------------------------------------------------------------------===// |
| |
| #include "ARMInstrInfo.h" |
| #include "ARM.h" |
| #include "ARMAddressingModes.h" |
| #include "ARMMachineFunctionInfo.h" |
| #include "llvm/ADT/STLExtras.h" |
| #include "llvm/CodeGen/LiveVariables.h" |
| #include "llvm/CodeGen/MachineFrameInfo.h" |
| #include "llvm/CodeGen/MachineInstrBuilder.h" |
| #include "llvm/CodeGen/MachineJumpTableInfo.h" |
| #include "llvm/MC/MCAsmInfo.h" |
| using namespace llvm; |
| |
| ARMInstrInfo::ARMInstrInfo(const ARMSubtarget &STI) |
| : ARMBaseInstrInfo(STI), RI(*this, STI) { |
| } |
| |
| unsigned ARMInstrInfo::getUnindexedOpcode(unsigned Opc) const { |
| switch (Opc) { |
| default: break; |
| case ARM::LDR_PRE: |
| case ARM::LDR_POST: |
| return ARM::LDRi12; |
| case ARM::LDRH_PRE: |
| case ARM::LDRH_POST: |
| return ARM::LDRH; |
| case ARM::LDRB_PRE: |
| case ARM::LDRB_POST: |
| return ARM::LDRBi12; |
| case ARM::LDRSH_PRE: |
| case ARM::LDRSH_POST: |
| return ARM::LDRSH; |
| case ARM::LDRSB_PRE: |
| case ARM::LDRSB_POST: |
| return ARM::LDRSB; |
| case ARM::STR_PRE: |
| case ARM::STR_POST: |
| return ARM::STRi12; |
| case ARM::STRH_PRE: |
| case ARM::STRH_POST: |
| return ARM::STRH; |
| case ARM::STRB_PRE: |
| case ARM::STRB_POST: |
| return ARM::STRBi12; |
| } |
| |
| return 0; |
| } |