| //===- Thumb1InstrInfo.cpp - Thumb-1 Instruction Information ----*- C++ -*-===// |
| // |
| // The LLVM Compiler Infrastructure |
| // |
| // This file is distributed under the University of Illinois Open Source |
| // License. See LICENSE.TXT for details. |
| // |
| //===----------------------------------------------------------------------===// |
| // |
| // This file contains the Thumb-1 implementation of the TargetInstrInfo class. |
| // |
| //===----------------------------------------------------------------------===// |
| |
| #include "Thumb1InstrInfo.h" |
| #include "ARM.h" |
| #include "ARMMachineFunctionInfo.h" |
| #include "llvm/CodeGen/MachineFrameInfo.h" |
| #include "llvm/CodeGen/MachineInstrBuilder.h" |
| #include "llvm/CodeGen/MachineRegisterInfo.h" |
| #include "llvm/CodeGen/MachineMemOperand.h" |
| #include "llvm/CodeGen/PseudoSourceValue.h" |
| #include "llvm/ADT/SmallVector.h" |
| #include "Thumb1InstrInfo.h" |
| |
| using namespace llvm; |
| |
| Thumb1InstrInfo::Thumb1InstrInfo(const ARMSubtarget &STI) |
| : ARMBaseInstrInfo(STI), RI(*this, STI) { |
| } |
| |
| unsigned Thumb1InstrInfo::getUnindexedOpcode(unsigned Opc) const { |
| return 0; |
| } |
| |
| void Thumb1InstrInfo::copyPhysReg(MachineBasicBlock &MBB, |
| MachineBasicBlock::iterator I, DebugLoc DL, |
| unsigned DestReg, unsigned SrcReg, |
| bool KillSrc) const { |
| bool tDest = ARM::tGPRRegClass.contains(DestReg); |
| bool tSrc = ARM::tGPRRegClass.contains(SrcReg); |
| unsigned Opc = ARM::tMOVgpr2gpr; |
| if (tDest && tSrc) |
| Opc = ARM::tMOVr; |
| else if (tSrc) |
| Opc = ARM::tMOVtgpr2gpr; |
| else if (tDest) |
| Opc = ARM::tMOVgpr2tgpr; |
| |
| BuildMI(MBB, I, DL, get(Opc), DestReg) |
| .addReg(SrcReg, getKillRegState(KillSrc)); |
| assert(ARM::GPRRegClass.contains(DestReg, SrcReg) && |
| "Thumb1 can only copy GPR registers"); |
| } |
| |
| void Thumb1InstrInfo:: |
| storeRegToStackSlot(MachineBasicBlock &MBB, MachineBasicBlock::iterator I, |
| unsigned SrcReg, bool isKill, int FI, |
| const TargetRegisterClass *RC, |
| const TargetRegisterInfo *TRI) const { |
| assert((RC == ARM::tGPRRegisterClass || |
| (TargetRegisterInfo::isPhysicalRegister(SrcReg) && |
| isARMLowRegister(SrcReg))) && "Unknown regclass!"); |
| |
| if (RC == ARM::tGPRRegisterClass || |
| (TargetRegisterInfo::isPhysicalRegister(SrcReg) && |
| isARMLowRegister(SrcReg))) { |
| DebugLoc DL; |
| if (I != MBB.end()) DL = I->getDebugLoc(); |
| |
| MachineFunction &MF = *MBB.getParent(); |
| MachineFrameInfo &MFI = *MF.getFrameInfo(); |
| MachineMemOperand *MMO = |
| MF.getMachineMemOperand( |
| MachinePointerInfo(PseudoSourceValue::getFixedStack(FI)), |
| MachineMemOperand::MOStore, |
| MFI.getObjectSize(FI), |
| MFI.getObjectAlignment(FI)); |
| AddDefaultPred(BuildMI(MBB, I, DL, get(ARM::tSpill)) |
| .addReg(SrcReg, getKillRegState(isKill)) |
| .addFrameIndex(FI).addImm(0).addMemOperand(MMO)); |
| } |
| } |
| |
| void Thumb1InstrInfo:: |
| loadRegFromStackSlot(MachineBasicBlock &MBB, MachineBasicBlock::iterator I, |
| unsigned DestReg, int FI, |
| const TargetRegisterClass *RC, |
| const TargetRegisterInfo *TRI) const { |
| assert((RC == ARM::tGPRRegisterClass || |
| (TargetRegisterInfo::isPhysicalRegister(DestReg) && |
| isARMLowRegister(DestReg))) && "Unknown regclass!"); |
| |
| if (RC == ARM::tGPRRegisterClass || |
| (TargetRegisterInfo::isPhysicalRegister(DestReg) && |
| isARMLowRegister(DestReg))) { |
| DebugLoc DL; |
| if (I != MBB.end()) DL = I->getDebugLoc(); |
| |
| MachineFunction &MF = *MBB.getParent(); |
| MachineFrameInfo &MFI = *MF.getFrameInfo(); |
| MachineMemOperand *MMO = |
| MF.getMachineMemOperand( |
| MachinePointerInfo(PseudoSourceValue::getFixedStack(FI)), |
| MachineMemOperand::MOLoad, |
| MFI.getObjectSize(FI), |
| MFI.getObjectAlignment(FI)); |
| AddDefaultPred(BuildMI(MBB, I, DL, get(ARM::tRestore), DestReg) |
| .addFrameIndex(FI).addImm(0).addMemOperand(MMO)); |
| } |
| } |