commit 23066288fdf4867f53f208f9aaf2952b1c049394
author Evan Cheng <evan.cheng@apple.com> Mon Oct 27 07:14:50 2008 +0000
committer Evan Cheng <evan.cheng@apple.com> Mon Oct 27 07:14:50 2008 +0000
tree 2bc4df159784221290c1aa16e2256ac55c523299
parent 0fd77a579bbed0fa06720474f1c5b2e3cd75004f

For now, don't split live intervals around x87 stack register barriers. FpGET_ST0_80 must be right after a call instruction (and ADJCALLSTACKUP) so we need to find a way to prevent reload of x87 registers between them.


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@58230 91177308-0d34-0410-b5e6-96231b3b80d8

lib/CodeGen/PreAllocSplitting.cpp

diff --git a/lib/CodeGen/PreAllocSplitting.cpp b/lib/CodeGen/PreAllocSplitting.cpp
index 547c528..33e3e80 100644
--- a/lib/CodeGen/PreAllocSplitting.cpp
+++ b/lib/CodeGen/PreAllocSplitting.cpp
@@ -659,6 +659,8 @@
   // by the current barrier.
   SmallVector<LiveInterval*, 8> Intervals;
   for (const TargetRegisterClass **RC = RCs; *RC; ++RC) {
+    if (TII->IgnoreRegisterClassBarriers(*RC))
+      continue;
     std::vector<unsigned> &VRs = MRI->getRegClassVirtRegs(*RC);
     for (unsigned i = 0, e = VRs.size(); i != e; ++i) {
       unsigned Reg = VRs[i];

lib/Target/X86/X86InstrInfo.cpp

diff --git a/lib/Target/X86/X86InstrInfo.cpp b/lib/Target/X86/X86InstrInfo.cpp
index 04f10c0..c08fdd8 100644
--- a/lib/Target/X86/X86InstrInfo.cpp
+++ b/lib/Target/X86/X86InstrInfo.cpp
@@ -2411,6 +2411,14 @@
   return false;
 }
 
+bool X86InstrInfo::
+IgnoreRegisterClassBarriers(const TargetRegisterClass *RC) const {
+  // FIXME: Ignore bariers of x87 stack registers for now. We can't
+  // allow any loads of these registers before FpGet_ST0_80.
+  return RC == &X86::CCRRegClass || RC == &X86::RFP32RegClass ||
+    RC == &X86::RFP64RegClass || RC == &X86::RFP80RegClass;
+}
+
 const TargetRegisterClass *X86InstrInfo::getPointerRegClass() const {
   const X86Subtarget *Subtarget = &TM.getSubtarget<X86Subtarget>();
   if (Subtarget->is64Bit())

lib/Target/X86/X86InstrInfo.h

diff --git a/lib/Target/X86/X86InstrInfo.h b/lib/Target/X86/X86InstrInfo.h
index 17be894..dc76f3e 100644
--- a/lib/Target/X86/X86InstrInfo.h
+++ b/lib/Target/X86/X86InstrInfo.h
@@ -405,6 +405,11 @@
   virtual
   bool ReverseBranchCondition(SmallVectorImpl<MachineOperand> &Cond) const;
 
+  /// IgnoreRegisterClassBarriers - Returns true if pre-register allocation
+  /// live interval splitting pass should ignore barriers of the specified
+  /// register class.
+  bool IgnoreRegisterClassBarriers(const TargetRegisterClass *RC) const;
+
   const TargetRegisterClass *getPointerRegClass() const;
 
   // getBaseOpcodeFor - This function returns the "base" X86 opcode for the

lib/Target/X86/X86RegisterInfo.h

diff --git a/lib/Target/X86/X86RegisterInfo.h b/lib/Target/X86/X86RegisterInfo.h
index 93e8613..25d7b07 100644
--- a/lib/Target/X86/X86RegisterInfo.h
+++ b/lib/Target/X86/X86RegisterInfo.h
@@ -94,6 +94,10 @@
 
   /// Code Generation virtual methods...
   /// 
+
+  /// getCrossCopyRegClass - Returns a legal register class to copy a register
+  /// in the specified class to or from. Returns NULL if it is possible to copy
+  /// between a two registers of the specified class.
   const TargetRegisterClass *
   getCrossCopyRegClass(const TargetRegisterClass *RC) const;