Add contexts to some of the MVT APIs. No functionality change yet, just the infrastructure work needed to get the contexts to where they need to be first.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@78759 91177308-0d34-0410-b5e6-96231b3b80d8
diff --git a/lib/Target/CellSPU/SPUISelDAGToDAG.cpp b/lib/Target/CellSPU/SPUISelDAGToDAG.cpp
index 9ae6722..a317706 100644
--- a/lib/Target/CellSPU/SPUISelDAGToDAG.cpp
+++ b/lib/Target/CellSPU/SPUISelDAGToDAG.cpp
@@ -726,8 +726,10 @@
&& OpVT == MVT::i64) {
SDValue Op0 = Op.getOperand(0);
EVT Op0VT = Op0.getValueType();
- EVT Op0VecVT = EVT::getVectorVT(Op0VT, (128 / Op0VT.getSizeInBits()));
- EVT OpVecVT = EVT::getVectorVT(OpVT, (128 / OpVT.getSizeInBits()));
+ EVT Op0VecVT = EVT::getVectorVT(*CurDAG->getContext(),
+ Op0VT, (128 / Op0VT.getSizeInBits()));
+ EVT OpVecVT = EVT::getVectorVT(*CurDAG->getContext(),
+ OpVT, (128 / OpVT.getSizeInBits()));
SDValue shufMask;
switch (Op0VT.getSimpleVT().SimpleTy) {
@@ -969,7 +971,8 @@
SDNode *
SPUDAGToDAGISel::SelectSHLi64(SDValue &Op, EVT OpVT) {
SDValue Op0 = Op.getOperand(0);
- EVT VecVT = EVT::getVectorVT(OpVT, (128 / OpVT.getSizeInBits()));
+ EVT VecVT = EVT::getVectorVT(*CurDAG->getContext(),
+ OpVT, (128 / OpVT.getSizeInBits()));
SDValue ShiftAmt = Op.getOperand(1);
EVT ShiftAmtVT = ShiftAmt.getValueType();
SDNode *VecOp0, *SelMask, *ZeroFill, *Shift = 0;
@@ -1034,7 +1037,8 @@
SDNode *
SPUDAGToDAGISel::SelectSRLi64(SDValue &Op, EVT OpVT) {
SDValue Op0 = Op.getOperand(0);
- EVT VecVT = EVT::getVectorVT(OpVT, (128 / OpVT.getSizeInBits()));
+ EVT VecVT = EVT::getVectorVT(*CurDAG->getContext(),
+ OpVT, (128 / OpVT.getSizeInBits()));
SDValue ShiftAmt = Op.getOperand(1);
EVT ShiftAmtVT = ShiftAmt.getValueType();
SDNode *VecOp0, *Shift = 0;
@@ -1100,7 +1104,8 @@
SDNode *
SPUDAGToDAGISel::SelectSRAi64(SDValue &Op, EVT OpVT) {
// Promote Op0 to vector
- EVT VecVT = EVT::getVectorVT(OpVT, (128 / OpVT.getSizeInBits()));
+ EVT VecVT = EVT::getVectorVT(*CurDAG->getContext(),
+ OpVT, (128 / OpVT.getSizeInBits()));
SDValue ShiftAmt = Op.getOperand(1);
EVT ShiftAmtVT = ShiftAmt.getValueType();
DebugLoc dl = Op.getDebugLoc();
@@ -1174,7 +1179,7 @@
SDNode *SPUDAGToDAGISel::SelectI64Constant(uint64_t Value64, EVT OpVT,
DebugLoc dl) {
- EVT OpVecVT = EVT::getVectorVT(OpVT, 2);
+ EVT OpVecVT = EVT::getVectorVT(*CurDAG->getContext(), OpVT, 2);
SDValue i64vec =
SPU::LowerV2I64Splat(OpVecVT, *CurDAG, Value64, dl);
diff --git a/lib/Target/CellSPU/SPUISelLowering.cpp b/lib/Target/CellSPU/SPUISelLowering.cpp
index 04a0eec..be3030d 100644
--- a/lib/Target/CellSPU/SPUISelLowering.cpp
+++ b/lib/Target/CellSPU/SPUISelLowering.cpp
@@ -101,7 +101,7 @@
TargetLowering::ArgListEntry Entry;
for (unsigned i = 0, e = Op.getNumOperands(); i != e; ++i) {
EVT ArgVT = Op.getOperand(i).getValueType();
- const Type *ArgTy = ArgVT.getTypeForEVT();
+ const Type *ArgTy = ArgVT.getTypeForEVT(*DAG.getContext());
Entry.Node = Op.getOperand(i);
Entry.Ty = ArgTy;
Entry.isSExt = isSigned;
@@ -112,7 +112,8 @@
TLI.getPointerTy());
// Splice the libcall in wherever FindInputOutputChains tells us to.
- const Type *RetTy = Op.getNode()->getValueType(0).getTypeForEVT();
+ const Type *RetTy =
+ Op.getNode()->getValueType(0).getTypeForEVT(*DAG.getContext());
std::pair<SDValue, SDValue> CallInfo =
TLI.LowerCallTo(InChain, RetTy, isSigned, !isSigned, false, false,
0, CallingConv::C, false,
@@ -683,7 +684,8 @@
// Convert the loaded v16i8 vector to the appropriate vector type
// specified by the operand:
- EVT vecVT = EVT::getVectorVT(InVT, (128 / InVT.getSizeInBits()));
+ EVT vecVT = EVT::getVectorVT(*DAG.getContext(),
+ InVT, (128 / InVT.getSizeInBits()));
result = DAG.getNode(SPUISD::VEC2PREFSLOT, dl, InVT,
DAG.getNode(ISD::BIT_CONVERT, dl, vecVT, result));
@@ -749,8 +751,10 @@
switch (SN->getAddressingMode()) {
case ISD::UNINDEXED: {
// The vector type we really want to load from the 16-byte chunk.
- EVT vecVT = EVT::getVectorVT(VT, (128 / VT.getSizeInBits())),
- stVecVT = EVT::getVectorVT(StVT, (128 / StVT.getSizeInBits()));
+ EVT vecVT = EVT::getVectorVT(*DAG.getContext(),
+ VT, (128 / VT.getSizeInBits())),
+ stVecVT = EVT::getVectorVT(*DAG.getContext(),
+ StVT, (128 / StVT.getSizeInBits()));
SDValue alignLoadVec;
SDValue basePtr = SN->getBasePtr();
@@ -2252,7 +2256,8 @@
*/
static SDValue LowerCTPOP(SDValue Op, SelectionDAG &DAG) {
EVT VT = Op.getValueType();
- EVT vecVT = EVT::getVectorVT(VT, (128 / VT.getSizeInBits()));
+ EVT vecVT = EVT::getVectorVT(*DAG.getContext(),
+ VT, (128 / VT.getSizeInBits()));
DebugLoc dl = Op.getDebugLoc();
switch (VT.getSimpleVT().SimpleTy) {
@@ -2575,7 +2580,8 @@
// Type to truncate to
EVT VT = Op.getValueType();
MVT simpleVT = VT.getSimpleVT();
- EVT VecVT = EVT::getVectorVT(VT, (128 / VT.getSizeInBits()));
+ EVT VecVT = EVT::getVectorVT(*DAG.getContext(),
+ VT, (128 / VT.getSizeInBits()));
DebugLoc dl = Op.getDebugLoc();
// Type to truncate from
diff --git a/lib/Target/PIC16/PIC16ISelLowering.cpp b/lib/Target/PIC16/PIC16ISelLowering.cpp
index 35f8f7c..d4cbc0a 100644
--- a/lib/Target/PIC16/PIC16ISelLowering.cpp
+++ b/lib/Target/PIC16/PIC16ISelLowering.cpp
@@ -399,7 +399,7 @@
TargetLowering::ArgListEntry Entry;
for (unsigned i = 0; i != NumOps; ++i) {
Entry.Node = Ops[i];
- Entry.Ty = Entry.Node.getValueType().getTypeForEVT();
+ Entry.Ty = Entry.Node.getValueType().getTypeForEVT(*DAG.getContext());
Entry.isSExt = isSigned;
Entry.isZExt = !isSigned;
Args.push_back(Entry);
@@ -407,7 +407,7 @@
SDValue Callee = DAG.getExternalSymbol(getPIC16LibcallName(Call), MVT::i16);
- const Type *RetTy = RetVT.getTypeForEVT();
+ const Type *RetTy = RetVT.getTypeForEVT(*DAG.getContext());
std::pair<SDValue,SDValue> CallInfo =
LowerCallTo(DAG.getEntryNode(), RetTy, isSigned, !isSigned, false,
false, 0, CallingConv::C, false,
@@ -691,7 +691,7 @@
SDValue &Lo, SDValue &Hi) {
SDNode *N = Op.getNode();
DebugLoc dl = N->getDebugLoc();
- EVT NewVT = getTypeToTransformTo(N->getValueType(0));
+ EVT NewVT = getTypeToTransformTo(*DAG.getContext(), N->getValueType(0));
// Extract the lo component.
Lo = DAG.getNode(ISD::EXTRACT_ELEMENT, dl, NewVT, Op,
diff --git a/lib/Target/PowerPC/PPCISelLowering.cpp b/lib/Target/PowerPC/PPCISelLowering.cpp
index caeba44..11c4093 100644
--- a/lib/Target/PowerPC/PPCISelLowering.cpp
+++ b/lib/Target/PowerPC/PPCISelLowering.cpp
@@ -1287,7 +1287,7 @@
// Lower to a call to __trampoline_setup(Trmp, TrampSize, FPtr, ctx_reg)
std::pair<SDValue, SDValue> CallResult =
- LowerCallTo(Chain, Op.getValueType().getTypeForEVT(),
+ LowerCallTo(Chain, Op.getValueType().getTypeForEVT(*DAG.getContext()),
false, false, false, false, 0, CallingConv::C, false,
/*isReturnValueUsed=*/true,
DAG.getExternalSymbol("__trampoline_setup", PtrVT),
diff --git a/lib/Target/XCore/XCoreISelLowering.cpp b/lib/Target/XCore/XCoreISelLowering.cpp
index 25077c7..e9ca3f5 100644
--- a/lib/Target/XCore/XCoreISelLowering.cpp
+++ b/lib/Target/XCore/XCoreISelLowering.cpp
@@ -373,7 +373,7 @@
return SDValue();
}
unsigned ABIAlignment = getTargetData()->
- getABITypeAlignment(LD->getMemoryVT().getTypeForEVT());
+ getABITypeAlignment(LD->getMemoryVT().getTypeForEVT(*DAG.getContext()));
// Leave aligned load alone.
if (LD->getAlignment() >= ABIAlignment) {
return SDValue();
@@ -469,7 +469,7 @@
return SDValue();
}
unsigned ABIAlignment = getTargetData()->
- getABITypeAlignment(ST->getMemoryVT().getTypeForEVT());
+ getABITypeAlignment(ST->getMemoryVT().getTypeForEVT(*DAG.getContext()));
// Leave aligned store alone.
if (ST->getAlignment() >= ABIAlignment) {
return SDValue();
@@ -1058,8 +1058,8 @@
if (StoreBits % 8) {
break;
}
- unsigned ABIAlignment = getTargetData()->
- getABITypeAlignment(ST->getMemoryVT().getTypeForEVT());
+ unsigned ABIAlignment = getTargetData()->getABITypeAlignment(
+ ST->getMemoryVT().getTypeForEVT(*DCI.DAG.getContext()));
unsigned Alignment = ST->getAlignment();
if (Alignment >= ABIAlignment) {
break;