Fix a few cases where the scheduler is not checking for phys reg copies. The scheduling node may have a NULL DAG node, yuck.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@122544 91177308-0d34-0410-b5e6-96231b3b80d8
diff --git a/lib/CodeGen/ScheduleDAG.cpp b/lib/CodeGen/ScheduleDAG.cpp
index 02e398f..83f2dd0 100644
--- a/lib/CodeGen/ScheduleDAG.cpp
+++ b/lib/CodeGen/ScheduleDAG.cpp
@@ -36,7 +36,7 @@
/// getInstrDesc helper to handle SDNodes.
const TargetInstrDesc *ScheduleDAG::getNodeDesc(const SDNode *Node) const {
- if (!Node->isMachineOpcode()) return NULL;
+ if (!Node || !Node->isMachineOpcode()) return NULL;
return &TII->get(Node->getMachineOpcode());
}
diff --git a/lib/CodeGen/SelectionDAG/ScheduleDAGRRList.cpp b/lib/CodeGen/SelectionDAG/ScheduleDAGRRList.cpp
index c93ef4d..d636804 100644
--- a/lib/CodeGen/SelectionDAG/ScheduleDAGRRList.cpp
+++ b/lib/CodeGen/SelectionDAG/ScheduleDAGRRList.cpp
@@ -435,6 +435,13 @@
/// Record this SUnit in the HazardRecognizer.
/// Does not update CurCycle.
void ScheduleDAGRRList::EmitNode(SUnit *SU) {
+ if (!EnableSchedCycles || HazardRec->getMaxLookAhead() == 0)
+ return;
+
+ // Check for phys reg copy.
+ if (!SU->getNode())
+ return;
+
switch (SU->getNode()->getOpcode()) {
default:
assert(SU->getNode()->isMachineOpcode() &&
@@ -645,13 +652,13 @@
/// CopyAndMoveSuccessors - Clone the specified node and move its scheduled
/// successors to the newly created node.
SUnit *ScheduleDAGRRList::CopyAndMoveSuccessors(SUnit *SU) {
- if (SU->getNode()->getGluedNode())
- return NULL;
-
SDNode *N = SU->getNode();
if (!N)
return NULL;
+ if (SU->getNode()->getGluedNode())
+ return NULL;
+
SUnit *NewSU;
bool TryUnfold = false;
for (unsigned i = 0, e = N->getNumValues(); i != e; ++i) {