Add ARM mode operand encoding information for ADDE/SUBE instructions.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@116412 91177308-0d34-0410-b5e6-96231b3b80d8
diff --git a/test/MC/ARM/simple-encoding.ll b/test/MC/ARM/simple-encoding.ll
index 997ccc8..01e9c98 100644
--- a/test/MC/ARM/simple-encoding.ll
+++ b/test/MC/ARM/simple-encoding.ll
@@ -55,4 +55,13 @@
%retval.0 = select i1 %cmp, i32 %b, i32 %c
ret i32 %retval.0
}
+
+define i64 @f6(i64 %a, i64 %b, i64 %c) nounwind readnone optsize ssp {
+entry:
+; CHECK: f6
+; CHECK: adds r0, r2, r0 @ encoding: [0x00,0x00,0x92,0xe0]
+; CHECK: adc r1, r3, r1 @ encoding: [0x01,0x10,0xa3,0xe0]
+ %add = add nsw i64 %b, %a
+ ret i64 %add
+}
declare void @llvm.trap() nounwind