commit 24cd3c4711333ca1e07cbdb34475bccfeb762bb6
author Daniel Dunbar <daniel@zuster.org> Thu Jul 16 22:08:25 2009 +0000
committer Daniel Dunbar <daniel@zuster.org> Thu Jul 16 22:08:25 2009 +0000
tree 5b515b1f8b90413f97bb5fe01524ee0289b844fb
parent efd280b4caf261b95551a317bb398a90d2e90011

Fix inverted preprocessor conditional.


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@76111 91177308-0d34-0410-b5e6-96231b3b80d8

lib/CodeGen/VirtRegRewriter.cpp

diff --git a/lib/CodeGen/VirtRegRewriter.cpp b/lib/CodeGen/VirtRegRewriter.cpp
index a859d80..61ea80b 100644
--- a/lib/CodeGen/VirtRegRewriter.cpp
+++ b/lib/CodeGen/VirtRegRewriter.cpp
@@ -491,7 +491,7 @@
                           const TargetRegisterInfo *TRI,
                           VirtRegMap &VRM) {
   MachineInstr *ReMatDefMI = VRM.getReMaterializedMI(Reg);
-#ifdef NDEBUG
+#ifndef NDEBUG
   const TargetInstrDesc &TID = ReMatDefMI->getDesc();
   assert(TID.getNumDefs() != 1 &&
          "Don't know how to remat instructions that define > 1 values!");