Add support for 12 bit displacements
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@75988 91177308-0d34-0410-b5e6-96231b3b80d8
diff --git a/lib/Target/SystemZ/SystemZOperands.td b/lib/Target/SystemZ/SystemZOperands.td
index 446e426..7ac6cc2 100644
--- a/lib/Target/SystemZ/SystemZOperands.td
+++ b/lib/Target/SystemZ/SystemZOperands.td
@@ -214,10 +214,14 @@
// Branch targets have OtherVT type.
def brtarget : Operand<OtherVT>;
-// Unigned i12
+// Unsigned i12
def u12imm : Operand<i32> {
- let PrintMethod = "printU16ImmOperand";
+ let PrintMethod = "printU12ImmOperand";
}
+def u12imm64 : Operand<i64> {
+ let PrintMethod = "printU12ImmOperand";
+}
+
// Signed i16
def s16imm : Operand<i32> {
let PrintMethod = "printS16ImmOperand";
@@ -262,8 +266,13 @@
//===----------------------------------------------------------------------===//
// rriaddr := reg + reg + imm
+def rriaddr12 : Operand<i64>,
+ ComplexPattern<i64, 3, "SelectAddrRRI12", [], []> {
+ let PrintMethod = "printRRIAddrOperand";
+ let MIOperandInfo = (ops ADDR64:$base, u12imm64:$disp, ADDR64:$index);
+}
def rriaddr : Operand<i64>,
- ComplexPattern<i64, 3, "SelectAddrRRI", [], []> {
+ ComplexPattern<i64, 3, "SelectAddrRRI20", [], []> {
let PrintMethod = "printRRIAddrOperand";
let MIOperandInfo = (ops ADDR64:$base, s20imm64:$disp, ADDR64:$index);
}