I'm introducing a new machine model to simultaneously allow simple
subtarget CPU descriptions and support new features of
MachineScheduler.
MachineModel has three categories of data:
1) Basic properties for coarse grained instruction cost model.
2) Scheduler Read/Write resources for simple per-opcode and operand cost model (TBD).
3) Instruction itineraties for detailed per-cycle reservation tables.
These will all live side-by-side. Any subtarget can use any
combination of them. Instruction itineraries will not change in the
near term. In the long run, I expect them to only be relevant for
in-order VLIW machines that have complex contraints and require a
precise scheduling/bundling model. Once itineraries are only actively
used by VLIW-ish targets, they could be replaced by something more
appropriate for those targets.
This tablegen backend rewrite sets things up for introducing
MachineModel type #2: per opcode/operand cost model.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@159891 91177308-0d34-0410-b5e6-96231b3b80d8
diff --git a/utils/TableGen/CodeGenTarget.h b/utils/TableGen/CodeGenTarget.h
index 85463da..2f8cee4 100644
--- a/utils/TableGen/CodeGenTarget.h
+++ b/utils/TableGen/CodeGenTarget.h
@@ -26,6 +26,7 @@
namespace llvm {
struct CodeGenRegister;
+class CodeGenSchedModels;
class CodeGenTarget;
// SelectionDAG node properties.
@@ -72,9 +73,12 @@
void ReadInstructions() const;
void ReadLegalValueTypes() const;
+ mutable CodeGenSchedModels *SchedModels;
+
mutable std::vector<const CodeGenInstruction*> InstrsByEnum;
public:
CodeGenTarget(RecordKeeper &Records);
+ ~CodeGenTarget();
Record *getTargetRecord() const { return TargetRec; }
const std::string &getName() const;
@@ -96,7 +100,7 @@
///
Record *getAsmParserVariant(unsigned i) const;
- /// getAsmParserVariantCount - Return the AssmblyParserVariant definition
+ /// getAsmParserVariantCount - Return the AssmblyParserVariant definition
/// available for this target.
///
unsigned getAsmParserVariantCount() const;
@@ -139,6 +143,8 @@
return false;
}
+ CodeGenSchedModels &getSchedModels() const;
+
private:
DenseMap<const Record*, CodeGenInstruction*> &getInstructions() const {
if (Instructions.empty()) ReadInstructions();