commit 28b51439f3b99bac332f32778ef26d000dc85301
author Evan Cheng <evan.cheng@apple.com> Tue Dec 05 19:50:18 2006 +0000
committer Evan Cheng <evan.cheng@apple.com> Tue Dec 05 19:50:18 2006 +0000
tree c82d851ab39889984f951fdeb012fbaa079bb033
parent f2d9ceb5b9dfbd5e50607bab4a87c1244bda0a71

- Switch X86-64 JIT to large code size model.
- Re-enable some codegen niceties for X86-64 static relocation model codegen.
- Clean ups, etc.


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@32238 91177308-0d34-0410-b5e6-96231b3b80d8

lib/Target/X86/X86ATTAsmPrinter.cpp

diff --git a/lib/Target/X86/X86ATTAsmPrinter.cpp b/lib/Target/X86/X86ATTAsmPrinter.cpp
index 79963ee..62f24db 100755
--- a/lib/Target/X86/X86ATTAsmPrinter.cpp
+++ b/lib/Target/X86/X86ATTAsmPrinter.cpp
@@ -156,7 +156,7 @@
 }
 
 void X86ATTAsmPrinter::printOperand(const MachineInstr *MI, unsigned OpNo,
-                                    const char *Modifier) {
+                                    const char *Modifier, bool NotRIPRel) {
   const MachineOperand &MO = MI->getOperand(OpNo);
   const MRegisterInfo &RI = *TM.getRegisterInfo();
   switch (MO.getType()) {
@@ -192,7 +192,7 @@
     if (X86PICStyle == PICStyle::Stub &&
         TM.getRelocationModel() == Reloc::PIC_)
       O << "-\"L" << getFunctionNumber() << "$pb\"";
-    if (isMemOp && Subtarget->is64Bit())
+    if (isMemOp && Subtarget->is64Bit() && !NotRIPRel)
       O << "(%rip)";
     return;
   }
@@ -210,7 +210,7 @@
     else if (Offset < 0)
       O << Offset;
 
-    if (isMemOp && Subtarget->is64Bit())
+    if (isMemOp && Subtarget->is64Bit() && !NotRIPRel)
       O << "(%rip)";
     return;
   }
@@ -267,8 +267,12 @@
 
     if (isMemOp && Subtarget->is64Bit()) {
       if (isExt && TM.getRelocationModel() != Reloc::Static)
-        O << "@GOTPCREL";
-      O << "(%rip)";
+        O << "@GOTPCREL(%rip)";
+      else if (!NotRIPRel)
+        // Use rip when possible to reduce code size, except when index or
+        // base register are also part of the address. e.g.
+        // foo(%rip)(%rcx,%rax,4) is not legal
+        O << "(%rip)";        
     }
 
     return;
@@ -329,10 +333,11 @@
     return;
   }
 
+  bool NotRIPRel = IndexReg.getReg() || BaseReg.getReg();
   if (DispSpec.isGlobalAddress() ||
       DispSpec.isConstantPoolIndex() ||
       DispSpec.isJumpTableIndex()) {
-    printOperand(MI, Op+3, "mem");
+    printOperand(MI, Op+3, "mem", NotRIPRel);
   } else {
     int DispVal = DispSpec.getImmedValue();
     if (DispVal || (!IndexReg.getReg() && !BaseReg.getReg()))