commit 2921916ffc7ce475ecb1896f487013bca5266059
author Andrew Lenharth <andrewl@lenharth.org> Mon Feb 07 06:31:44 2005 +0000
committer Andrew Lenharth <andrewl@lenharth.org> Mon Feb 07 06:31:44 2005 +0000
tree b563a4ef18c4a3fb1d74bfb17076cf9cc4c02dda
parent 06342c3484dc6ff606db72206f9668276af13a64

copytoreg fix


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@20063 91177308-0d34-0410-b5e6-96231b3b80d8

lib/Target/Alpha/AlphaISelPattern.cpp

diff --git a/lib/Target/Alpha/AlphaISelPattern.cpp b/lib/Target/Alpha/AlphaISelPattern.cpp
index 6e4704c..a173fa3 100644
--- a/lib/Target/Alpha/AlphaISelPattern.cpp
+++ b/lib/Target/Alpha/AlphaISelPattern.cpp
@@ -424,7 +424,7 @@
       else
 	Result = ExprMap[N.getValue(0)] = MakeReg(N.getValue(0).getValueType());
 
-      //DestType = N.getValue(0).getValueType();
+      DestType = N.getValue(0).getValueType();
 
       SDOperand Chain   = N.getOperand(0);
       SDOperand Address = N.getOperand(1);
@@ -503,27 +503,24 @@
         {
           AlphaLowering.restoreGP(BB);
           BuildMI(BB, Alpha::LDS_SYM, 1, Tmp1).addGlobalAddress(cast<GlobalAddressSDNode>(Address)->getGlobal());
-          BuildMI(BB, Alpha::CVTST, 1, Result).addReg(Tmp1);
          }
       else if (ConstantPoolSDNode *CP = dyn_cast<ConstantPoolSDNode>(N.getOperand(1))) 
         {
           AlphaLowering.restoreGP(BB);
           BuildMI(BB, Alpha::LDS_SYM, 1, Tmp1).addConstantPoolIndex(CP->getIndex());
-          BuildMI(BB, Alpha::CVTST, 1, Result).addReg(Tmp1);
         }
       else if(Address.getOpcode() == ISD::FrameIndex)
         {
           Tmp2 = cast<FrameIndexSDNode>(Address)->getIndex();
           BuildMI(BB, Alpha::LDS, 2, Tmp1).addFrameIndex(Tmp2).addReg(Alpha::F31);
-          BuildMI(BB, Alpha::CVTST, 1, Result).addReg(Tmp1);
         }
       else
         {
           long offset;
           SelectAddr(Address, Tmp2, offset);
           BuildMI(BB, Alpha::LDS, 1, Tmp1).addImm(offset).addReg(Tmp2);
-          BuildMI(BB, Alpha::CVTST, 1, Result).addReg(Tmp1);
         }
+      BuildMI(BB, Alpha::CVTST, 1, Result).addReg(Tmp1);
       return Result;
     }
 
@@ -1222,7 +1219,10 @@
     Tmp2 = cast<RegSDNode>(N)->getReg();
     
     if (Tmp1 != Tmp2) {
-      BuildMI(BB, Alpha::BIS, 2, Tmp2).addReg(Tmp1).addReg(Tmp1);
+      if (N.getOperand(1).getValueType() == MVT::f64 || N.getOperand(1).getValueType() == MVT::f32)
+        BuildMI(BB, Alpha::CPYS, 2, Tmp2).addReg(Tmp1).addReg(Tmp1);
+      else
+        BuildMI(BB, Alpha::BIS, 2, Tmp2).addReg(Tmp1).addReg(Tmp1);
     }
     return;