Fix a long-standing wart in the code generator: two-address instruction lowering
actually *removes* one of the operands, instead of just assigning both operands
the same register. This make reasoning about instructions unnecessarily complex,
because you need to know if you are before or after register allocation to match
up operand #'s with the target description file.
Changing this also gets rid of a bunch of hacky code in various places.
This patch also includes changes to fold loads into cmp/test instructions in
the X86 backend, along with a significant simplification to the X86 spill
folding code.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@30108 91177308-0d34-0410-b5e6-96231b3b80d8
diff --git a/lib/CodeGen/RegAllocSimple.cpp b/lib/CodeGen/RegAllocSimple.cpp
index b28e21a..ad09f82 100644
--- a/lib/CodeGen/RegAllocSimple.cpp
+++ b/lib/CodeGen/RegAllocSimple.cpp
@@ -203,17 +203,13 @@
physReg = getFreeReg(virtualReg);
} else {
// must be same register number as the first operand
- // This maps a = b + c into b += c, and saves b into a's spot
+ // This maps a = b + c into b = b + c, and saves b into a's spot.
assert(MI->getOperand(1).isRegister() &&
MI->getOperand(1).getReg() &&
MI->getOperand(1).isUse() &&
"Two address instruction invalid!");
physReg = MI->getOperand(1).getReg();
- spillVirtReg(MBB, next(MI), virtualReg, physReg);
- MI->getOperand(1).setDef();
- MI->RemoveOperand(0);
- break; // This is the last operand to process
}
spillVirtReg(MBB, next(MI), virtualReg, physReg);
} else {