commit 2a6e6161422154ea44f9e653e2d0bbfc3942af2b
author Bob Wilson <bob.wilson@apple.com> Thu Sep 23 23:42:37 2010 +0000
committer Bob Wilson <bob.wilson@apple.com> Thu Sep 23 23:42:37 2010 +0000
tree 64b52802ffcff0e3267ff1cab2cd5aebdf8568b8
parent 453900814e5245fd823b2b24ee9da9b5e8b4bfc4

Set alignment operand for NEON VST instructions.


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@114709 91177308-0d34-0410-b5e6-96231b3b80d8

lib/Target/ARM/ARMISelDAGToDAG.cpp

diff --git a/lib/Target/ARM/ARMISelDAGToDAG.cpp b/lib/Target/ARM/ARMISelDAGToDAG.cpp
index c81f950..bcaf662 100644
--- a/lib/Target/ARM/ARMISelDAGToDAG.cpp
+++ b/lib/Target/ARM/ARMISelDAGToDAG.cpp
@@ -1002,6 +1002,24 @@
   return CurDAG->getMachineNode(TargetOpcode::REG_SEQUENCE, dl, VT, Ops, 8);
 }
 
+/// GetVLDSTAlign - Get the alignment (in bytes) for the alignment operand
+/// of a NEON VLD or VST instruction.  The supported values depend on the
+/// number of registers being loaded.
+static unsigned GetVLDSTAlign(SDNode *N, unsigned NumVecs, bool is64BitVector) {
+  unsigned NumRegs = NumVecs;
+  if (!is64BitVector && NumVecs < 3)
+    NumRegs *= 2;
+
+  unsigned Alignment = cast<MemIntrinsicSDNode>(N)->getAlignment();
+  if (Alignment >= 32 && NumRegs == 4)
+    return 32;
+  if (Alignment >= 16 && (NumRegs == 2 || NumRegs == 4))
+    return 16;
+  if (Alignment >= 8)
+    return 8;
+  return 0;
+}
+
 SDNode *ARMDAGToDAGISel::SelectVLD(SDNode *N, unsigned NumVecs,
                                    unsigned *DOpcodes, unsigned *QOpcodes0,
                                    unsigned *QOpcodes1) {
@@ -1016,20 +1034,7 @@
   EVT VT = N->getValueType(0);
   bool is64BitVector = VT.is64BitVector();
 
-  // Set the alignment.  The supported values depend on the number of
-  // registers being loaded.
-  unsigned NumRegs = NumVecs;
-  if (!is64BitVector && NumVecs < 3)
-    NumRegs *= 2;
-  unsigned Alignment = cast<MemIntrinsicSDNode>(N)->getAlignment();
-  if (Alignment >= 32 && NumRegs == 4)
-    Alignment = 32;
-  else if (Alignment >= 16 && (NumRegs == 2 || NumRegs == 4))
-    Alignment = 16;
-  else if (Alignment >= 8)
-    Alignment = 8;
-  else
-    Alignment = 0;
+  unsigned Alignment = GetVLDSTAlign(N, NumVecs, is64BitVector);
   Align = CurDAG->getTargetConstant(Alignment, MVT::i32);
 
   unsigned OpcodeIndex;
@@ -1143,6 +1148,9 @@
   EVT VT = N->getOperand(3).getValueType();
   bool is64BitVector = VT.is64BitVector();
 
+  unsigned Alignment = GetVLDSTAlign(N, NumVecs, is64BitVector);
+  Align = CurDAG->getTargetConstant(Alignment, MVT::i32);
+
   unsigned OpcodeIndex;
   switch (VT.getSimpleVT().SimpleTy) {
   default: llvm_unreachable("unhandled vst type");