commit 2a79a0927c479b69316aa275c1f79c74d20e8040
author Chris Lattner <sabre@nondot.org> Wed Oct 30 00:58:19 2002 +0000
committer Chris Lattner <sabre@nondot.org> Wed Oct 30 00:58:19 2002 +0000
tree 3d1f1a36ad52e296b846c2bc92401b9e7593373a
parent e5f5221b5ee04eaffdd76c196c32b82ca4b9a332

Use MRegisterInfo, if available, to print symbolic register names


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@4438 91177308-0d34-0410-b5e6-96231b3b80d8

lib/CodeGen/MachineInstr.cpp

diff --git a/lib/CodeGen/MachineInstr.cpp b/lib/CodeGen/MachineInstr.cpp
index 1fde26a..961e568 100644
--- a/lib/CodeGen/MachineInstr.cpp
+++ b/lib/CodeGen/MachineInstr.cpp
@@ -7,6 +7,7 @@
 #include "llvm/Value.h"
 #include "llvm/Target/MachineInstrInfo.h"  // FIXME: shouldn't need this!
 #include "llvm/Target/TargetMachine.h"
+#include "llvm/Target/MRegisterInfo.h"
 using std::cerr;
 
 // Global variable holding an array of descriptors for machine instructions.
@@ -191,14 +192,20 @@
     return os << (void*) val << ")";              // print address only
 }
 
-static inline std::ostream&
-OutputReg(std::ostream &os, unsigned int regNum)
-{
-  return os << "%mreg(" << regNum << ")";
+static inline void OutputReg(std::ostream &os, unsigned RegNo,
+                             const MRegisterInfo *MRI = 0) {
+  if (MRI) {
+    if (RegNo < MRegisterInfo::FirstVirtualRegister)
+      os << "%" << MRI->get(RegNo).Name;
+    else
+      os << "%reg" << RegNo;
+  } else
+    os << "%mreg(" << RegNo << ")";
 }
 
 static void print(const MachineOperand &MO, std::ostream &OS,
                   const TargetMachine &TM) {
+  const MRegisterInfo *MRI = TM.getRegisterInfo();
   bool CloseParen = true;
   if (MO.opHiBits32())
     OS << "%lm(";
@@ -220,18 +227,18 @@
         OS << "==";
     }
     if (MO.hasAllocatedReg())
-      OutputReg(OS, MO.getAllocatedRegNum());
+      OutputReg(OS, MO.getAllocatedRegNum(), MRI);
     break;
   case MachineOperand::MO_CCRegister:
     OS << "%ccreg";
     OutputValue(OS, MO.getVRegValue());
     if (MO.hasAllocatedReg()) {
       OS << "==";
-      OutputReg(OS, MO.getAllocatedRegNum());
+      OutputReg(OS, MO.getAllocatedRegNum(), MRI);
     }
     break;
   case MachineOperand::MO_MachineRegister:
-    OutputReg(OS, MO.getMachineRegNum());
+    OutputReg(OS, MO.getMachineRegNum(), MRI);
     break;
   case MachineOperand::MO_SignExtendedImmed:
     OS << (long)MO.getImmedValue();