[mips][msa] Added support for matching fadd, fdiv, flog2, fmul, frint, fsqrt, and fsub from normal IR (i.e. not intrinsics)
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@190512 91177308-0d34-0410-b5e6-96231b3b80d8
diff --git a/lib/Target/Mips/MipsSEISelLowering.cpp b/lib/Target/Mips/MipsSEISelLowering.cpp
index 2de21ea..c307aa7 100644
--- a/lib/Target/Mips/MipsSEISelLowering.cpp
+++ b/lib/Target/Mips/MipsSEISelLowering.cpp
@@ -175,6 +175,16 @@
setOperationAction(ISD::LOAD, Ty, Legal);
setOperationAction(ISD::STORE, Ty, Legal);
setOperationAction(ISD::BITCAST, Ty, Legal);
+
+ if (Ty != MVT::v8f16) {
+ setOperationAction(ISD::FADD, Ty, Legal);
+ setOperationAction(ISD::FDIV, Ty, Legal);
+ setOperationAction(ISD::FLOG2, Ty, Legal);
+ setOperationAction(ISD::FMUL, Ty, Legal);
+ setOperationAction(ISD::FRINT, Ty, Legal);
+ setOperationAction(ISD::FSQRT, Ty, Legal);
+ setOperationAction(ISD::FSUB, Ty, Legal);
+ }
}
bool
@@ -823,6 +833,16 @@
return Result;
}
+static SDValue lowerMSAUnaryIntr(SDValue Op, SelectionDAG &DAG, unsigned Opc) {
+ SDLoc DL(Op);
+ SDValue Value = Op->getOperand(1);
+ EVT ResTy = Op->getValueType(0);
+
+ SDValue Result = DAG.getNode(Opc, DL, ResTy, Value);
+
+ return Result;
+}
+
SDValue MipsSETargetLowering::lowerINTRINSIC_WO_CHAIN(SDValue Op,
SelectionDAG &DAG) const {
switch (cast<ConstantSDNode>(Op->getOperand(0))->getZExtValue()) {
@@ -889,6 +909,27 @@
case Intrinsic::mips_div_u_w:
case Intrinsic::mips_div_u_d:
return lowerMSABinaryIntr(Op, DAG, ISD::UDIV);
+ case Intrinsic::mips_fadd_w:
+ case Intrinsic::mips_fadd_d:
+ return lowerMSABinaryIntr(Op, DAG, ISD::FADD);
+ case Intrinsic::mips_fdiv_w:
+ case Intrinsic::mips_fdiv_d:
+ return lowerMSABinaryIntr(Op, DAG, ISD::FDIV);
+ case Intrinsic::mips_flog2_w:
+ case Intrinsic::mips_flog2_d:
+ return lowerMSAUnaryIntr(Op, DAG, ISD::FLOG2);
+ case Intrinsic::mips_fmul_w:
+ case Intrinsic::mips_fmul_d:
+ return lowerMSABinaryIntr(Op, DAG, ISD::FMUL);
+ case Intrinsic::mips_frint_w:
+ case Intrinsic::mips_frint_d:
+ return lowerMSAUnaryIntr(Op, DAG, ISD::FRINT);
+ case Intrinsic::mips_fsqrt_w:
+ case Intrinsic::mips_fsqrt_d:
+ return lowerMSAUnaryIntr(Op, DAG, ISD::FSQRT);
+ case Intrinsic::mips_fsub_w:
+ case Intrinsic::mips_fsub_d:
+ return lowerMSABinaryIntr(Op, DAG, ISD::FSUB);
}
}