Split IMPLICIT_DEF into IMPLICIT_DEF_GPR and IMPLICIT_DEF_FP, so that the
instructions take a consistent reg class. Implement ISD::UNDEF in the dag->dag
selector to generate this, fixing UnitTests/2003-07-06-IntOverflow.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@23028 91177308-0d34-0410-b5e6-96231b3b80d8
diff --git a/lib/Target/PowerPC/PPCBranchSelector.cpp b/lib/Target/PowerPC/PPCBranchSelector.cpp
index b80ab5e..9a29eec 100644
--- a/lib/Target/PowerPC/PPCBranchSelector.cpp
+++ b/lib/Target/PowerPC/PPCBranchSelector.cpp
@@ -40,7 +40,8 @@
// minor pessimization that saves us from having to worry about
// keeping the offsets up to date later when we emit long branch glue.
return 12;
- case PPC::IMPLICIT_DEF: // no asm emitted
+ case PPC::IMPLICIT_DEF_GPR: // no asm emitted
+ case PPC::IMPLICIT_DEF_FP: // no asm emitted
return 0;
default:
break;
diff --git a/lib/Target/PowerPC/PPCCodeEmitter.cpp b/lib/Target/PowerPC/PPCCodeEmitter.cpp
index a52935a..25cbda5 100644
--- a/lib/Target/PowerPC/PPCCodeEmitter.cpp
+++ b/lib/Target/PowerPC/PPCCodeEmitter.cpp
@@ -124,7 +124,8 @@
default:
emitWord(getBinaryCodeForInstr(*I));
break;
- case PPC::IMPLICIT_DEF:
+ case PPC::IMPLICIT_DEF_GPR:
+ case PPC::IMPLICIT_DEF_FP:
break; // pseudo opcode, no side effects
case PPC::MovePCtoLR:
assert(0 && "CodeEmitter does not support MovePCtoLR instruction");
diff --git a/lib/Target/PowerPC/PPCISelDAGToDAG.cpp b/lib/Target/PowerPC/PPCISelDAGToDAG.cpp
index b6ce27a..161d17d 100644
--- a/lib/Target/PowerPC/PPCISelDAGToDAG.cpp
+++ b/lib/Target/PowerPC/PPCISelDAGToDAG.cpp
@@ -469,7 +469,6 @@
std::cerr << "\n";
abort();
case ISD::EntryToken: // These leaves remain the same.
- case ISD::UNDEF:
return Op;
case ISD::TokenFactor: {
SDOperand New;
@@ -525,6 +524,12 @@
}
break;
}
+ case ISD::UNDEF:
+ if (N->getValueType(0) == MVT::i32)
+ CurDAG->SelectNodeTo(N, MVT::i32, PPC::IMPLICIT_DEF_GPR);
+ else
+ CurDAG->SelectNodeTo(N, N->getValueType(0), PPC::IMPLICIT_DEF_FP);
+ break;
case ISD::GlobalAddress: {
GlobalValue *GV = cast<GlobalAddressSDNode>(N)->getGlobal();
SDOperand Tmp;
diff --git a/lib/Target/PowerPC/PPCISelPattern.cpp b/lib/Target/PowerPC/PPCISelPattern.cpp
index 4e753d1..22082a4 100644
--- a/lib/Target/PowerPC/PPCISelPattern.cpp
+++ b/lib/Target/PowerPC/PPCISelPattern.cpp
@@ -830,7 +830,10 @@
Node->dump(); std::cerr << '\n';
assert(0 && "Node not handled!\n");
case ISD::UNDEF:
- BuildMI(BB, PPC::IMPLICIT_DEF, 0, Result);
+ if (Node->getValueType(0) == MVT::i32)
+ BuildMI(BB, PPC::IMPLICIT_DEF_GPR, 0, Result);
+ else
+ BuildMI(BB, PPC::IMPLICIT_DEF_FP, 0, Result);
return Result;
case ISD::DYNAMIC_STACKALLOC:
// Generate both result values. FIXME: Need a better commment here?
@@ -1872,8 +1875,11 @@
return;
case ISD::ImplicitDef:
Select(N.getOperand(0));
- BuildMI(BB, PPC::IMPLICIT_DEF, 0,
- cast<RegisterSDNode>(N.getOperand(1))->getReg());
+ Tmp1 = cast<RegisterSDNode>(N.getOperand(1))->getReg();
+ if (N.getOperand(1).getValueType() == MVT::i32)
+ BuildMI(BB, PPC::IMPLICIT_DEF_GPR, 0, Tmp1);
+ else
+ BuildMI(BB, PPC::IMPLICIT_DEF_FP, 0, Tmp1);
return;
case ISD::RET:
switch (N.getNumOperands()) {
diff --git a/lib/Target/PowerPC/PPCInstrInfo.td b/lib/Target/PowerPC/PPCInstrInfo.td
index a42ccf3..b0a8b3b 100644
--- a/lib/Target/PowerPC/PPCInstrInfo.td
+++ b/lib/Target/PowerPC/PPCInstrInfo.td
@@ -64,7 +64,8 @@
def ADJCALLSTACKDOWN : Pseudo<(ops u16imm), "; ADJCALLSTACKDOWN">;
def ADJCALLSTACKUP : Pseudo<(ops u16imm), "; ADJCALLSTACKUP">;
}
-def IMPLICIT_DEF : Pseudo<(ops variable_ops), "; IMPLICIT_DEF">;
+def IMPLICIT_DEF_GPR : Pseudo<(ops GPRC:$rD), "; $rD = IMPLICIT_DEF_GPRC">;
+def IMPLICIT_DEF_FP : Pseudo<(ops FPRC:$rD), "; %rD = IMPLICIT_DEF_FP">;
let Defs = [LR] in
def MovePCtoLR : Pseudo<(ops piclabel:$label), "bl $label">;