Change MachineInstrBuilder::addReg() to take a flag instead of a list of
booleans. This gives a better indication of what the "addReg()" is
doing. Remembering what all of those booleans mean isn't easy, especially if you
aren't spending all of your time in that code.
I took Jakob's suggestion and made it illegal to pass in "true" for the
flag. This should hopefully prevent any unintended misuse of this (by reverting
to the old way of using addReg()).
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@71722 91177308-0d34-0410-b5e6-96231b3b80d8
diff --git a/lib/Target/ARM/ARMInstrInfo.cpp b/lib/Target/ARM/ARMInstrInfo.cpp
index 235d1d1..8e678a8 100644
--- a/lib/Target/ARM/ARMInstrInfo.cpp
+++ b/lib/Target/ARM/ARMInstrInfo.cpp
@@ -546,23 +546,23 @@
ARMFunctionInfo *AFI = MF.getInfo<ARMFunctionInfo>();
assert (!AFI->isThumbFunction());
AddDefaultPred(BuildMI(MBB, I, DL, get(ARM::STR))
- .addReg(SrcReg, false, false, isKill)
+ .addReg(SrcReg, getKillRegState(isKill))
.addFrameIndex(FI).addReg(0).addImm(0));
} else if (RC == ARM::tGPRRegisterClass) {
MachineFunction &MF = *MBB.getParent();
ARMFunctionInfo *AFI = MF.getInfo<ARMFunctionInfo>();
assert (AFI->isThumbFunction());
BuildMI(MBB, I, DL, get(ARM::tSpill))
- .addReg(SrcReg, false, false, isKill)
+ .addReg(SrcReg, getKillRegState(isKill))
.addFrameIndex(FI).addImm(0);
} else if (RC == ARM::DPRRegisterClass) {
AddDefaultPred(BuildMI(MBB, I, DL, get(ARM::FSTD))
- .addReg(SrcReg, false, false, isKill)
+ .addReg(SrcReg, getKillRegState(isKill))
.addFrameIndex(FI).addImm(0));
} else {
assert(RC == ARM::SPRRegisterClass && "Unknown regclass!");
AddDefaultPred(BuildMI(MBB, I, DL, get(ARM::FSTS))
- .addReg(SrcReg, false, false, isKill)
+ .addReg(SrcReg, getKillRegState(isKill))
.addFrameIndex(FI).addImm(0));
}
}
@@ -579,7 +579,7 @@
if (AFI->isThumbFunction()) {
Opc = Addr[0].isFI() ? ARM::tSpill : ARM::tSTR;
MachineInstrBuilder MIB =
- BuildMI(MF, DL, get(Opc)).addReg(SrcReg, false, false, isKill);
+ BuildMI(MF, DL, get(Opc)).addReg(SrcReg, getKillRegState(isKill));
for (unsigned i = 0, e = Addr.size(); i != e; ++i)
MIB.addOperand(Addr[i]);
NewMIs.push_back(MIB);
@@ -594,7 +594,7 @@
}
MachineInstrBuilder MIB =
- BuildMI(MF, DL, get(Opc)).addReg(SrcReg, false, false, isKill);
+ BuildMI(MF, DL, get(Opc)).addReg(SrcReg, getKillRegState(isKill));
for (unsigned i = 0, e = Addr.size(); i != e; ++i)
MIB.addOperand(Addr[i]);
AddDefaultPred(MIB);
@@ -681,7 +681,7 @@
unsigned Reg = CSI[i-1].getReg();
// Add the callee-saved register as live-in. It's killed at the spill.
MBB.addLiveIn(Reg);
- MIB.addReg(Reg, false/*isDef*/,false/*isImp*/,true/*isKill*/);
+ MIB.addReg(Reg, RegState::Kill);
}
return true;
}
@@ -733,13 +733,13 @@
unsigned SrcReg = MI->getOperand(1).getReg();
bool isKill = MI->getOperand(1).isKill();
NewMI = BuildMI(MF, MI->getDebugLoc(), get(ARM::STR))
- .addReg(SrcReg, false, false, isKill)
+ .addReg(SrcReg, getKillRegState(isKill))
.addFrameIndex(FI).addReg(0).addImm(0).addImm(Pred).addReg(PredReg);
} else { // move -> load
unsigned DstReg = MI->getOperand(0).getReg();
bool isDead = MI->getOperand(0).isDead();
NewMI = BuildMI(MF, MI->getDebugLoc(), get(ARM::LDR))
- .addReg(DstReg, true, false, false, isDead)
+ .addReg(DstReg, RegState::Define | getDeadRegState(isDead))
.addFrameIndex(FI).addReg(0).addImm(0).addImm(Pred).addReg(PredReg);
}
break;
@@ -755,7 +755,7 @@
// tSpill cannot take a high register operand.
break;
NewMI = BuildMI(MF, MI->getDebugLoc(), get(ARM::tSpill))
- .addReg(SrcReg, false, false, isKill)
+ .addReg(SrcReg, getKillRegState(isKill))
.addFrameIndex(FI).addImm(0);
} else { // move -> load
unsigned DstReg = MI->getOperand(0).getReg();
@@ -764,7 +764,7 @@
break;
bool isDead = MI->getOperand(0).isDead();
NewMI = BuildMI(MF, MI->getDebugLoc(), get(ARM::tRestore))
- .addReg(DstReg, true, false, false, isDead)
+ .addReg(DstReg, RegState::Define | getDeadRegState(isDead))
.addFrameIndex(FI).addImm(0);
}
break;
@@ -792,13 +792,13 @@
unsigned SrcReg = MI->getOperand(1).getReg();
bool isKill = MI->getOperand(1).isKill();
NewMI = BuildMI(MF, MI->getDebugLoc(), get(ARM::FSTD))
- .addReg(SrcReg, false, false, isKill)
+ .addReg(SrcReg, getKillRegState(isKill))
.addFrameIndex(FI).addImm(0).addImm(Pred).addReg(PredReg);
} else { // move -> load
unsigned DstReg = MI->getOperand(0).getReg();
bool isDead = MI->getOperand(0).isDead();
NewMI = BuildMI(MF, MI->getDebugLoc(), get(ARM::FLDD))
- .addReg(DstReg, true, false, false, isDead)
+ .addReg(DstReg, RegState::Define | getDeadRegState(isDead))
.addFrameIndex(FI).addImm(0).addImm(Pred).addReg(PredReg);
}
break;