commit 2b9378646d35526fe6ccef7b76b888d15e9c3a80
author Chris Lattner <sabre@nondot.org> Wed Jan 12 07:33:20 2005 +0000
committer Chris Lattner <sabre@nondot.org> Wed Jan 12 07:33:20 2005 +0000
tree b49af9984a97ddeeb2037fc1de7e285bba93ac9b
parent 48034fd9f10490daca2fdd4e3801e13c26849ca7

Fix a major miscompilation where we were overwriting the scale reg.


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@19511 91177308-0d34-0410-b5e6-96231b3b80d8

lib/Target/X86/X86ISelPattern.cpp

diff --git a/lib/Target/X86/X86ISelPattern.cpp b/lib/Target/X86/X86ISelPattern.cpp
index a796045..b3a93b1 100644
--- a/lib/Target/X86/X86ISelPattern.cpp
+++ b/lib/Target/X86/X86ISelPattern.cpp
@@ -469,7 +469,7 @@
     AM.Disp += cast<ConstantSDNode>(N)->getValue();
     return false;
   case ISD::SHL:
-    if (AM.IndexReg == 0 || AM.Scale == 1)
+    if (AM.IndexReg == 0 && AM.Scale == 1)
       if (ConstantSDNode *CN = dyn_cast<ConstantSDNode>(N.Val->getOperand(1))) {
         unsigned Val = CN->getValue();
         if (Val == 1 || Val == 2 || Val == 3) {