| commit | 2c614c5c699fed503b93e85ea0cb48811843c3c7 | [log] [tgz] |
|---|---|---|
| author | Evan Cheng <evan.cheng@apple.com> | Wed Jun 06 10:17:05 2007 +0000 |
| committer | Evan Cheng <evan.cheng@apple.com> | Wed Jun 06 10:17:05 2007 +0000 |
| tree | eecbea4aa3ddfe506ad8d57762231c18f35fabb8 | |
| parent | 7a655479ae56f8b71ea266f3fde3f25a7bc7e8d4 [diff] [blame] |
Mark these instructions clobbersPred. They modify the condition code register. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@37468 91177308-0d34-0410-b5e6-96231b3b80d8
diff --git a/lib/Target/ARM/ARMInstrVFP.td b/lib/Target/ARM/ARMInstrVFP.td index c0428e9..73a3b37 100644 --- a/lib/Target/ARM/ARMInstrVFP.td +++ b/lib/Target/ARM/ARMInstrVFP.td
@@ -277,7 +277,7 @@ // FMSRR: GPR -> SPR - +let clobbersPred = 1 in def FMSTAT : ASI<(ops), "fmstat", "", [(arm_fmstat)]>; // FMXR: GPR -> VFP Sstem reg