Code Model: Improve the accuracy of the zext/sext/trunc vector cost estimation.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@167412 91177308-0d34-0410-b5e6-96231b3b80d8
diff --git a/lib/Target/TargetTransformImpl.cpp b/lib/Target/TargetTransformImpl.cpp
index 4b427a2..ca0dd9a 100644
--- a/lib/Target/TargetTransformImpl.cpp
+++ b/lib/Target/TargetTransformImpl.cpp
@@ -101,7 +101,7 @@
case AtomicRMW: return 0;
case Trunc: return ISD::TRUNCATE;
case ZExt: return ISD::ZERO_EXTEND;
- case SExt: return ISD::SEXTLOAD;
+ case SExt: return ISD::SIGN_EXTEND;
case FPToUI: return ISD::FP_TO_UINT;
case FPToSI: return ISD::FP_TO_SINT;
case UIToFP: return ISD::UINT_TO_FP;
@@ -235,9 +235,17 @@
SrcLT.second.getSizeInBits() == DstLT.second.getSizeInBits()) {
// Bitcast between types that are legalized to the same type are free.
- if (Opcode == Instruction::BitCast)
+ if (Opcode == Instruction::BitCast || Opcode == Instruction::Trunc)
return 0;
+ // Assume that Zext is done using AND.
+ if (Opcode == Instruction::ZExt)
+ return 1;
+
+ // Assume that sext is done using SHL and SRA.
+ if (Opcode == Instruction::SExt)
+ return 2;
+
// Just check the op cost. If the operation is legal then assume it costs
// 1 and multiply by the type-legalization overhead.
if (!TLI->isOperationExpand(ISD, DstLT.second))
@@ -310,7 +318,6 @@
return 1;
}
-/// Returns the expected cost of Vector Insert and Extract.
unsigned VectorTargetTransformImpl::getVectorInstrCost(unsigned Opcode,
Type *Val,
unsigned Index) const {