commit 2d5aff761d32b7f4fddc982e9444d20af48f080b
author Nate Begeman <natebegeman@mac.com> Wed Oct 19 18:42:01 2005 +0000
committer Nate Begeman <natebegeman@mac.com> Wed Oct 19 18:42:01 2005 +0000
tree ab00451f6cfd50628e1ad4e046b1fd527f87f61e
parent 886eb391704333cb0f24fad32f95da43371b9407

Write patterns for the various shl and srl patterns that don't involve
doing something clever.


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@23824 91177308-0d34-0410-b5e6-96231b3b80d8

lib/Target/PowerPC/PPCISelDAGToDAG.cpp

diff --git a/lib/Target/PowerPC/PPCISelDAGToDAG.cpp b/lib/Target/PowerPC/PPCISelDAGToDAG.cpp
index 7cc9269..430efd8 100644
--- a/lib/Target/PowerPC/PPCISelDAGToDAG.cpp
+++ b/lib/Target/PowerPC/PPCISelDAGToDAG.cpp
@@ -1214,51 +1214,28 @@
   case ISD::SHL: {
     unsigned Imm, SH, MB, ME;
     if (isOpcWithIntImmediate(N->getOperand(0).Val, ISD::AND, Imm) &&
-        isRotateAndMask(N, Imm, true, SH, MB, ME))
+        isRotateAndMask(N, Imm, true, SH, MB, ME)) {
       CurDAG->SelectNodeTo(N, PPC::RLWINM, MVT::i32, 
                            Select(N->getOperand(0).getOperand(0)),
                            getI32Imm(SH), getI32Imm(MB), getI32Imm(ME));
-    else if (isIntImmediate(N->getOperand(1), Imm)) {
-      if (N->getValueType(0) == MVT::i64)
-        CurDAG->SelectNodeTo(N, PPC::RLDICR, MVT::i64, Select(N->getOperand(0)),
-                             getI32Imm(Imm), getI32Imm(63-Imm));
-      else
-        CurDAG->SelectNodeTo(N, PPC::RLWINM, MVT::i32, Select(N->getOperand(0)),
-                             getI32Imm(Imm), getI32Imm(0), getI32Imm(31-Imm));
-    } else {
-      if (N->getValueType(0) == MVT::i64)
-        CurDAG->SelectNodeTo(N, PPC::SLD, MVT::i64, Select(N->getOperand(0)),
-                             Select(N->getOperand(1)));
-      else
-        CurDAG->SelectNodeTo(N, PPC::SLW, MVT::i32, Select(N->getOperand(0)),
-                             Select(N->getOperand(1)));
+      return SDOperand(N, 0);
     }
-    return SDOperand(N, 0);
+    
+    // Other cases are autogenerated.
+    break;
   }
   case ISD::SRL: {
     unsigned Imm, SH, MB, ME;
     if (isOpcWithIntImmediate(N->getOperand(0).Val, ISD::AND, Imm) &&
-        isRotateAndMask(N, Imm, true, SH, MB, ME))
+        isRotateAndMask(N, Imm, true, SH, MB, ME)) { 
       CurDAG->SelectNodeTo(N, PPC::RLWINM, MVT::i32, 
                            Select(N->getOperand(0).getOperand(0)),
                            getI32Imm(SH & 0x1F), getI32Imm(MB), getI32Imm(ME));
-    else if (isIntImmediate(N->getOperand(1), Imm)) {
-      if (N->getValueType(0) == MVT::i64)
-        CurDAG->SelectNodeTo(N, PPC::RLDICL, MVT::i64, Select(N->getOperand(0)),
-                             getI32Imm(64-Imm), getI32Imm(Imm));
-      else
-        CurDAG->SelectNodeTo(N, PPC::RLWINM, MVT::i32, Select(N->getOperand(0)),
-                             getI32Imm((32-Imm) & 0x1F), getI32Imm(Imm),
-                             getI32Imm(31));
-    } else {
-      if (N->getValueType(0) == MVT::i64)
-        CurDAG->SelectNodeTo(N, PPC::SRD, MVT::i64, Select(N->getOperand(0)),
-                             Select(N->getOperand(1)));
-      else
-        CurDAG->SelectNodeTo(N, PPC::SRW, MVT::i32, Select(N->getOperand(0)),
-                             Select(N->getOperand(1)));
+      return SDOperand(N, 0);
     }
-    return SDOperand(N, 0);
+    
+    // Other cases are autogenerated.
+    break;
   }
   case ISD::FNEG: {
     SDOperand Val = Select(N->getOperand(0));