commit 2df5e554e262c9c2b31b401387fee8678d16cec2
author Daniel Dunbar <daniel@zuster.org> Thu Jul 16 23:02:46 2009 +0000
committer Daniel Dunbar <daniel@zuster.org> Thu Jul 16 23:02:46 2009 +0000
tree bf079afc24b992f6af2fdb59e3c6b072437d35c0
parent 49e3182c97ec8a026eb4d8d714d697310d72f701

Disable this assert for now, it is firing on an llvm-gcc bootstrap. :(


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@76123 91177308-0d34-0410-b5e6-96231b3b80d8

lib/CodeGen/VirtRegRewriter.cpp

diff --git a/lib/CodeGen/VirtRegRewriter.cpp b/lib/CodeGen/VirtRegRewriter.cpp
index 61ea80b..2213c65 100644
--- a/lib/CodeGen/VirtRegRewriter.cpp
+++ b/lib/CodeGen/VirtRegRewriter.cpp
@@ -491,11 +491,13 @@
                           const TargetRegisterInfo *TRI,
                           VirtRegMap &VRM) {
   MachineInstr *ReMatDefMI = VRM.getReMaterializedMI(Reg);
+#if 0
 #ifndef NDEBUG
   const TargetInstrDesc &TID = ReMatDefMI->getDesc();
   assert(TID.getNumDefs() != 1 &&
          "Don't know how to remat instructions that define > 1 values!");
 #endif
+#endif
   TII->reMaterialize(MBB, MII, DestReg,
                      ReMatDefMI->getOperand(0).getSubReg(), ReMatDefMI);
   MachineInstr *NewMI = prior(MII);