Naming consistency.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@30878 91177308-0d34-0410-b5e6-96231b3b80d8
diff --git a/lib/CodeGen/SelectionDAG/DAGCombiner.cpp b/lib/CodeGen/SelectionDAG/DAGCombiner.cpp
index 96456aa..262b023 100644
--- a/lib/CodeGen/SelectionDAG/DAGCombiner.cpp
+++ b/lib/CodeGen/SelectionDAG/DAGCombiner.cpp
@@ -1077,7 +1077,7 @@
// fold (zext_inreg (extload x)) -> (zextload x)
if (ISD::isEXTLoad(N0.Val)) {
LoadSDNode *LN0 = cast<LoadSDNode>(N0);
- MVT::ValueType EVT = LN0->getLoadVT();
+ MVT::ValueType EVT = LN0->getLoadedVT();
// If we zero all the possible extended bits, then we can turn this into
// a zextload if we are running before legalize or the operation is legal.
if (TLI.MaskedValueIsZero(N1, ~0ULL << MVT::getSizeInBits(EVT)) &&
@@ -1093,7 +1093,7 @@
// fold (zext_inreg (sextload x)) -> (zextload x) iff load has one use
if (ISD::isSEXTLoad(N0.Val) && N0.hasOneUse()) {
LoadSDNode *LN0 = cast<LoadSDNode>(N0);
- MVT::ValueType EVT = LN0->getLoadVT();
+ MVT::ValueType EVT = LN0->getLoadedVT();
// If we zero all the possible extended bits, then we can turn this into
// a zextload if we are running before legalize or the operation is legal.
if (TLI.MaskedValueIsZero(N1, ~0ULL << MVT::getSizeInBits(EVT)) &&
@@ -1123,7 +1123,7 @@
else
EVT = MVT::Other;
- LoadedVT = LN0->getLoadVT();
+ LoadedVT = LN0->getLoadedVT();
if (EVT != MVT::Other && LoadedVT > EVT &&
(!AfterLegalize || TLI.isLoadXLegal(ISD::ZEXTLOAD, EVT))) {
MVT::ValueType PtrType = N0.getOperand(1).getValueType();
@@ -1874,7 +1874,7 @@
// fold (sext ( extload x)) -> (sext (truncate (sextload x)))
if ((ISD::isSEXTLoad(N0.Val) || ISD::isEXTLoad(N0.Val)) && N0.hasOneUse()) {
LoadSDNode *LN0 = cast<LoadSDNode>(N0);
- MVT::ValueType EVT = LN0->getLoadVT();
+ MVT::ValueType EVT = LN0->getLoadedVT();
SDOperand ExtLoad = DAG.getExtLoad(ISD::SEXTLOAD, VT, LN0->getChain(),
LN0->getBasePtr(), LN0->getSrcValue(),
LN0->getSrcValueOffset(), EVT);
@@ -1943,7 +1943,7 @@
// fold (zext ( extload x)) -> (zext (truncate (zextload x)))
if ((ISD::isZEXTLoad(N0.Val) || ISD::isEXTLoad(N0.Val)) && N0.hasOneUse()) {
LoadSDNode *LN0 = cast<LoadSDNode>(N0);
- MVT::ValueType EVT = LN0->getLoadVT();
+ MVT::ValueType EVT = LN0->getLoadedVT();
SDOperand ExtLoad = DAG.getExtLoad(ISD::ZEXTLOAD, VT, LN0->getChain(),
LN0->getBasePtr(), LN0->getSrcValue(),
LN0->getSrcValueOffset(), EVT);
@@ -2014,7 +2014,7 @@
if (N0.getOpcode() == ISD::LOAD && !ISD::isNON_EXTLoad(N0.Val) &&
N0.hasOneUse()) {
LoadSDNode *LN0 = cast<LoadSDNode>(N0);
- MVT::ValueType EVT = LN0->getLoadVT();
+ MVT::ValueType EVT = LN0->getLoadedVT();
SDOperand ExtLoad = DAG.getExtLoad(LN0->getExtensionType(), VT,
LN0->getChain(), LN0->getBasePtr(),
LN0->getSrcValue(),
@@ -2069,7 +2069,7 @@
// fold (sext_inreg (extload x)) -> (sextload x)
if (ISD::isEXTLoad(N0.Val) &&
- EVT == cast<LoadSDNode>(N0)->getLoadVT() &&
+ EVT == cast<LoadSDNode>(N0)->getLoadedVT() &&
(!AfterLegalize || TLI.isLoadXLegal(ISD::SEXTLOAD, EVT))) {
LoadSDNode *LN0 = cast<LoadSDNode>(N0);
SDOperand ExtLoad = DAG.getExtLoad(ISD::SEXTLOAD, VT, LN0->getChain(),
@@ -2081,7 +2081,7 @@
}
// fold (sext_inreg (zextload x)) -> (sextload x) iff load has one use
if (ISD::isZEXTLoad(N0.Val) && N0.hasOneUse() &&
- EVT == cast<LoadSDNode>(N0)->getLoadVT() &&
+ EVT == cast<LoadSDNode>(N0)->getLoadedVT() &&
(!AfterLegalize || TLI.isLoadXLegal(ISD::SEXTLOAD, EVT))) {
LoadSDNode *LN0 = cast<LoadSDNode>(N0);
SDOperand ExtLoad = DAG.getExtLoad(ISD::SEXTLOAD, VT, LN0->getChain(),
@@ -3282,7 +3282,7 @@
LoadSDNode *RLD = cast<LoadSDNode>(RHS);
// If this is an EXTLOAD, the VT's must match.
- if (LLD->getLoadVT() == RLD->getLoadVT()) {
+ if (LLD->getLoadedVT() == RLD->getLoadedVT()) {
// FIXME: this conflates two src values, discarding one. This is not
// the right thing to do, but nothing uses srcvalues now. When they do,
// turn SrcValue into a list of locations.
@@ -3307,7 +3307,7 @@
TheSelect->getValueType(0),
LLD->getChain(), Addr, LLD->getSrcValue(),
LLD->getSrcValueOffset(),
- LLD->getLoadVT());
+ LLD->getLoadedVT());
}
// Users of the select now use the result of the load.
CombineTo(TheSelect, Load);
diff --git a/lib/CodeGen/SelectionDAG/LegalizeDAG.cpp b/lib/CodeGen/SelectionDAG/LegalizeDAG.cpp
index b7262d6..c0d3076 100644
--- a/lib/CodeGen/SelectionDAG/LegalizeDAG.cpp
+++ b/lib/CodeGen/SelectionDAG/LegalizeDAG.cpp
@@ -1364,7 +1364,7 @@
AddLegalizedOperand(SDOperand(Node, 1), Tmp4);
return Op.ResNo ? Tmp4 : Tmp3;
} else {
- MVT::ValueType SrcVT = LD->getLoadVT();
+ MVT::ValueType SrcVT = LD->getLoadedVT();
switch (TLI.getLoadXAction(ExtType, SrcVT)) {
default: assert(0 && "This action is not supported yet!");
case TargetLowering::Promote:
@@ -3228,7 +3228,7 @@
Result = DAG.getExtLoad(ExtType, NVT,
LD->getChain(), LD->getBasePtr(),
LD->getSrcValue(), LD->getSrcValueOffset(),
- LD->getLoadVT());
+ LD->getLoadedVT());
// Remember that we legalized the chain.
AddLegalizedOperand(Op.getValue(1), LegalizeOp(Result.getValue(1)));
break;
@@ -4431,7 +4431,7 @@
if (!TLI.isLittleEndian())
std::swap(Lo, Hi);
} else {
- MVT::ValueType EVT = LD->getLoadVT();
+ MVT::ValueType EVT = LD->getLoadedVT();
if (EVT == NVT)
Lo = DAG.getLoad(NVT, Ch, Ptr, LD->getSrcValue(),
diff --git a/lib/CodeGen/SelectionDAG/SelectionDAG.cpp b/lib/CodeGen/SelectionDAG/SelectionDAG.cpp
index f2e1423..8147324 100644
--- a/lib/CodeGen/SelectionDAG/SelectionDAG.cpp
+++ b/lib/CodeGen/SelectionDAG/SelectionDAG.cpp
@@ -457,7 +457,7 @@
if (const LoadSDNode *LD = dyn_cast<LoadSDNode>(N)) {
ID.AddInteger(LD->getAddressingMode());
ID.AddInteger(LD->getExtensionType());
- ID.AddInteger(LD->getLoadVT());
+ ID.AddInteger(LD->getLoadedVT());
ID.AddPointer(LD->getSrcValue());
ID.AddInteger(LD->getSrcValueOffset());
ID.AddInteger(LD->getAlignment());
@@ -2715,7 +2715,7 @@
break;
}
if (doExt)
- std::cerr << MVT::getValueTypeString(LD->getLoadVT()) << ">";
+ std::cerr << MVT::getValueTypeString(LD->getLoadedVT()) << ">";
if (LD->getAddressingMode() == ISD::PRE_INDEXED)
std::cerr << " <pre>";
diff --git a/lib/CodeGen/SelectionDAG/SelectionDAGPrinter.cpp b/lib/CodeGen/SelectionDAG/SelectionDAGPrinter.cpp
index 75c0cb3..486f054 100644
--- a/lib/CodeGen/SelectionDAG/SelectionDAGPrinter.cpp
+++ b/lib/CodeGen/SelectionDAG/SelectionDAGPrinter.cpp
@@ -145,7 +145,7 @@
break;
}
if (doExt)
- Op = Op + MVT::getValueTypeString(LD->getLoadVT()) + ">";
+ Op = Op + MVT::getValueTypeString(LD->getLoadedVT()) + ">";
if (LD->getAddressingMode() == ISD::PRE_INDEXED)
Op = Op + "<pre>";
diff --git a/lib/CodeGen/SelectionDAG/TargetLowering.cpp b/lib/CodeGen/SelectionDAG/TargetLowering.cpp
index 73cefc4..0183678 100644
--- a/lib/CodeGen/SelectionDAG/TargetLowering.cpp
+++ b/lib/CodeGen/SelectionDAG/TargetLowering.cpp
@@ -555,7 +555,7 @@
case ISD::LOAD: {
if (ISD::isZEXTLoad(Op.Val)) {
LoadSDNode *LD = cast<LoadSDNode>(Op);
- MVT::ValueType VT = LD->getLoadVT();
+ MVT::ValueType VT = LD->getLoadedVT();
KnownZero |= ~MVT::getIntVTBitMask(VT) & DemandedMask;
}
break;
@@ -896,7 +896,7 @@
case ISD::LOAD: {
if (ISD::isZEXTLoad(Op.Val)) {
LoadSDNode *LD = cast<LoadSDNode>(Op);
- MVT::ValueType VT = LD->getLoadVT();
+ MVT::ValueType VT = LD->getLoadedVT();
KnownZero |= ~MVT::getIntVTBitMask(VT) & Mask;
}
return;
@@ -1205,10 +1205,10 @@
switch (ExtType) {
default: break;
case ISD::SEXTLOAD: // '17' bits known
- Tmp = MVT::getSizeInBits(LD->getLoadVT());
+ Tmp = MVT::getSizeInBits(LD->getLoadedVT());
return VTBits-Tmp+1;
case ISD::ZEXTLOAD: // '16' bits known
- Tmp = MVT::getSizeInBits(LD->getLoadVT());
+ Tmp = MVT::getSizeInBits(LD->getLoadedVT());
return VTBits-Tmp;
}
}