commit 2ef773acebb57ff01b72bd1b2d5a06b8a942fdbc
author Scott Michel <scottm@aero.org> Tue Jan 06 03:36:14 2009 +0000
committer Scott Michel <scottm@aero.org> Tue Jan 06 03:36:14 2009 +0000
tree 749b9dddfb5b61c1c59f3199aa63706b167f0c5d
parent 17526c38c1e219e829ea0250271eec432fbca6f6

CellSPU:
- Fix bugs 3194, 3195: i128 load/stores produce correct code (although, we
  need to ensure that i128 is 16-byte aligned in real life), and 128 zero-
  extends are supported.
- New td file: SPU128InstrInfo.td: this is where all new i128 support should
  be put in the future.
- Continue to hammer on i64 operations and test cases; ensure that the only
  remaining problem will be i64 mul.


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@61784 91177308-0d34-0410-b5e6-96231b3b80d8

lib/Target/CellSPU/SPUCallingConv.td

diff --git a/lib/Target/CellSPU/SPUCallingConv.td b/lib/Target/CellSPU/SPUCallingConv.td
index 4bad198..5213e42 100644
--- a/lib/Target/CellSPU/SPUCallingConv.td
+++ b/lib/Target/CellSPU/SPUCallingConv.td
@@ -21,10 +21,11 @@
 
 // Return-value convention for Cell SPU: Everything can be passed back via $3:
 def RetCC_SPU : CallingConv<[
-  CCIfType<[i8],  CCAssignToReg<[R3]>>,
-  CCIfType<[i16], CCAssignToReg<[R3]>>,
-  CCIfType<[i32], CCAssignToReg<[R3]>>,
-  CCIfType<[i64], CCAssignToReg<[R3]>>,
+  CCIfType<[i8],   CCAssignToReg<[R3]>>,
+  CCIfType<[i16],  CCAssignToReg<[R3]>>,
+  CCIfType<[i32],  CCAssignToReg<[R3]>>,
+  CCIfType<[i64],  CCAssignToReg<[R3]>>,
+  CCIfType<[i128], CCAssignToReg<[R3]>>,
   CCIfType<[f32, f64], CCAssignToReg<[R3]>>,
   CCIfType<[v16i8, v8i16, v4i32, v2i64, v4f32, v2f64], CCAssignToReg<[R3]>>
 ]>;