Match tablegen isel changes.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@29549 91177308-0d34-0410-b5e6-96231b3b80d8
diff --git a/lib/Target/Sparc/SparcISelDAGToDAG.cpp b/lib/Target/Sparc/SparcISelDAGToDAG.cpp
index 1004109..a0f52f0 100644
--- a/lib/Target/Sparc/SparcISelDAGToDAG.cpp
+++ b/lib/Target/Sparc/SparcISelDAGToDAG.cpp
@@ -25,6 +25,7 @@
#include "llvm/Target/TargetLowering.h"
#include "llvm/Support/Debug.h"
#include <iostream>
+#include <queue>
#include <set>
using namespace llvm;
@@ -1001,9 +1002,6 @@
// Select target instructions for the DAG.
DAG.setRoot(SelectRoot(DAG.getRoot()));
- CodeGenMap.clear();
- HandleMap.clear();
- ReplaceMap.clear();
DAG.RemoveDeadNodes();
// Emit machine code to BB.
@@ -1083,21 +1081,14 @@
return; // Already selected.
}
- // If this has already been converted, use it.
- std::map<SDOperand, SDOperand>::iterator CGMI = CodeGenMap.find(Op);
- if (CGMI != CodeGenMap.end()) {
- Result = CGMI->second;
- return;
- }
-
switch (N->getOpcode()) {
default: break;
case ISD::SDIV:
case ISD::UDIV: {
// FIXME: should use a custom expander to expose the SRA to the dag.
SDOperand DivLHS, DivRHS;
- Select(DivLHS, N->getOperand(0));
- Select(DivRHS, N->getOperand(1));
+ AddToQueue(DivLHS, N->getOperand(0));
+ AddToQueue(DivRHS, N->getOperand(1));
// Set the Y register to the high-part.
SDOperand TopPart;
@@ -1119,8 +1110,8 @@
case ISD::MULHS: {
// FIXME: Handle mul by immediate.
SDOperand MulLHS, MulRHS;
- Select(MulLHS, N->getOperand(0));
- Select(MulRHS, N->getOperand(1));
+ AddToQueue(MulLHS, N->getOperand(0));
+ AddToQueue(MulRHS, N->getOperand(1));
unsigned Opcode = N->getOpcode() == ISD::MULHU ? SP::UMULrr : SP::SMULrr;
SDNode *Mul = CurDAG->getTargetNode(Opcode, MVT::i32, MVT::Flag,
MulLHS, MulRHS);