Convert RegisterAllocator interface to opaque pass type, so that users do not
need to know _anything_ about RegAlloc to use it. Well in the end maybe.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@1681 91177308-0d34-0410-b5e6-96231b3b80d8
diff --git a/lib/CodeGen/RegAlloc/PhyRegAlloc.cpp b/lib/CodeGen/RegAlloc/PhyRegAlloc.cpp
index 7efb469..46f045c 100644
--- a/lib/CodeGen/RegAlloc/PhyRegAlloc.cpp
+++ b/lib/CodeGen/RegAlloc/PhyRegAlloc.cpp
@@ -32,21 +32,35 @@
clEnumValN(RA_DEBUG_Verbose, "v", "enable extra debug output"), 0);
-bool RegisterAllocation::runOnMethod(Method *M) {
- if (DEBUG_RA)
- cerr << "\n******************** Method "<< M->getName()
- << " ********************\n";
+//----------------------------------------------------------------------------
+// RegisterAllocation pass front end...
+//----------------------------------------------------------------------------
+namespace {
+ class RegisterAllocator : public MethodPass {
+ TargetMachine &Target;
+ public:
+ inline RegisterAllocator(TargetMachine &T) : Target(T) {}
- MethodLiveVarInfo LVI(M); // Analyze live varaibles
- LVI.analyze();
-
- PhyRegAlloc PRA(M, Target, &LVI); // allocate registers
- PRA.allocateRegisters();
-
- if (DEBUG_RA) cerr << "\nRegister allocation complete!\n";
- return false;
+ bool runOnMethod(Method *M) {
+ if (DEBUG_RA)
+ cerr << "\n******************** Method "<< M->getName()
+ << " ********************\n";
+
+ MethodLiveVarInfo LVI(M); // Analyze live varaibles
+ LVI.analyze();
+
+ PhyRegAlloc PRA(M, Target, &LVI); // allocate registers
+ PRA.allocateRegisters();
+
+ if (DEBUG_RA) cerr << "\nRegister allocation complete!\n";
+ return false;
+ }
+ };
}
+MethodPass *getRegisterAllocator(TargetMachine &T) {
+ return new RegisterAllocator(T);
+}
//----------------------------------------------------------------------------
// Constructor: Init local composite objects and create register classes.
diff --git a/lib/Target/SparcV9/RegAlloc/PhyRegAlloc.cpp b/lib/Target/SparcV9/RegAlloc/PhyRegAlloc.cpp
index 7efb469..46f045c 100644
--- a/lib/Target/SparcV9/RegAlloc/PhyRegAlloc.cpp
+++ b/lib/Target/SparcV9/RegAlloc/PhyRegAlloc.cpp
@@ -32,21 +32,35 @@
clEnumValN(RA_DEBUG_Verbose, "v", "enable extra debug output"), 0);
-bool RegisterAllocation::runOnMethod(Method *M) {
- if (DEBUG_RA)
- cerr << "\n******************** Method "<< M->getName()
- << " ********************\n";
+//----------------------------------------------------------------------------
+// RegisterAllocation pass front end...
+//----------------------------------------------------------------------------
+namespace {
+ class RegisterAllocator : public MethodPass {
+ TargetMachine &Target;
+ public:
+ inline RegisterAllocator(TargetMachine &T) : Target(T) {}
- MethodLiveVarInfo LVI(M); // Analyze live varaibles
- LVI.analyze();
-
- PhyRegAlloc PRA(M, Target, &LVI); // allocate registers
- PRA.allocateRegisters();
-
- if (DEBUG_RA) cerr << "\nRegister allocation complete!\n";
- return false;
+ bool runOnMethod(Method *M) {
+ if (DEBUG_RA)
+ cerr << "\n******************** Method "<< M->getName()
+ << " ********************\n";
+
+ MethodLiveVarInfo LVI(M); // Analyze live varaibles
+ LVI.analyze();
+
+ PhyRegAlloc PRA(M, Target, &LVI); // allocate registers
+ PRA.allocateRegisters();
+
+ if (DEBUG_RA) cerr << "\nRegister allocation complete!\n";
+ return false;
+ }
+ };
}
+MethodPass *getRegisterAllocator(TargetMachine &T) {
+ return new RegisterAllocator(T);
+}
//----------------------------------------------------------------------------
// Constructor: Init local composite objects and create register classes.
diff --git a/lib/Target/SparcV9/SparcV9TargetMachine.cpp b/lib/Target/SparcV9/SparcV9TargetMachine.cpp
index b4e0694..91e51d8 100644
--- a/lib/Target/SparcV9/SparcV9TargetMachine.cpp
+++ b/lib/Target/SparcV9/SparcV9TargetMachine.cpp
@@ -260,7 +260,7 @@
//PM.add(new InstructionScheduling(*this));
- PM.add(new RegisterAllocation(*this));
+ PM.add(getRegisterAllocator(*this));
//PM.add(new OptimizeLeafProcedures());
//PM.add(new DeleteFallThroughBranches());