rename hasVariableOperands() -> isVariadic(). Add some comments.
Evan, please review the comments I added to getNumDefs to make sure
that they are accurate, thx.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@45687 91177308-0d34-0410-b5e6-96231b3b80d8
diff --git a/utils/TableGen/CodeGenInstruction.cpp b/utils/TableGen/CodeGenInstruction.cpp
index ea01d1b..daab065 100644
--- a/utils/TableGen/CodeGenInstruction.cpp
+++ b/utils/TableGen/CodeGenInstruction.cpp
@@ -99,7 +99,7 @@
mayHaveSideEffects = R->getValueAsBit("mayHaveSideEffects");
neverHasSideEffects = R->getValueAsBit("neverHasSideEffects");
hasOptionalDef = false;
- hasVariableNumberOfOperands = false;
+ isVariadic = false;
if (mayHaveSideEffects && neverHasSideEffects)
throw R->getName() +
@@ -159,7 +159,7 @@
else if (Rec->isSubClassOf("OptionalDefOperand"))
hasOptionalDef = true;
} else if (Rec->getName() == "variable_ops") {
- hasVariableNumberOfOperands = true;
+ isVariadic = true;
continue;
} else if (!Rec->isSubClassOf("RegisterClass") &&
Rec->getName() != "ptr_rc")
diff --git a/utils/TableGen/CodeGenInstruction.h b/utils/TableGen/CodeGenInstruction.h
index 351a880..6f7a19e 100644
--- a/utils/TableGen/CodeGenInstruction.h
+++ b/utils/TableGen/CodeGenInstruction.h
@@ -99,7 +99,7 @@
bool isReMaterializable;
bool hasDelaySlot;
bool usesCustomDAGSchedInserter;
- bool hasVariableNumberOfOperands;
+ bool isVariadic;
bool hasCtrlDep;
bool isNotDuplicable;
bool hasOptionalDef;
diff --git a/utils/TableGen/DAGISelEmitter.cpp b/utils/TableGen/DAGISelEmitter.cpp
index bd8d210..8502d61 100644
--- a/utils/TableGen/DAGISelEmitter.cpp
+++ b/utils/TableGen/DAGISelEmitter.cpp
@@ -835,7 +835,7 @@
if (InstPatNode && InstPatNode->getOperator()->getName() == "set") {
InstPatNode = InstPatNode->getChild(InstPatNode->getNumChildren()-1);
}
- bool HasVarOps = isRoot && II.hasVariableNumberOfOperands;
+ bool HasVarOps = isRoot && II.isVariadic;
// FIXME: fix how we deal with physical register operands.
bool HasImpInputs = isRoot && Inst.getNumImpOperands() > 0;
bool HasImpResults = isRoot && DstRegs.size() > 0;
diff --git a/utils/TableGen/InstrInfoEmitter.cpp b/utils/TableGen/InstrInfoEmitter.cpp
index 77ee860..51896b8 100644
--- a/utils/TableGen/InstrInfoEmitter.cpp
+++ b/utils/TableGen/InstrInfoEmitter.cpp
@@ -320,9 +320,9 @@
if (Inst.hasOptionalDef) OS << "|M_HAS_OPTIONAL_DEF";
if (Inst.usesCustomDAGSchedInserter)
OS << "|M_USES_CUSTOM_DAG_SCHED_INSERTION";
- if (Inst.hasVariableNumberOfOperands) OS << "|M_VARIABLE_OPS";
- if (Inst.mayHaveSideEffects) OS << "|M_MAY_HAVE_SIDE_EFFECTS";
- if (NeverHasSideEffects) OS << "|M_NEVER_HAS_SIDE_EFFECTS";
+ if (Inst.isVariadic) OS << "|M_VARIADIC";
+ if (Inst.mayHaveSideEffects) OS << "|M_MAY_HAVE_SIDE_EFFECTS";
+ if (NeverHasSideEffects) OS << "|M_NEVER_HAS_SIDE_EFFECTS";
OS << ", 0";
// Emit all of the target-specific flags...