finegrainify namespacification, fix 80col prob
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@11445 91177308-0d34-0410-b5e6-96231b3b80d8
diff --git a/lib/Target/X86/X86ISelSimple.cpp b/lib/Target/X86/X86ISelSimple.cpp
index d4a5ac2..6129c74 100644
--- a/lib/Target/X86/X86ISelSimple.cpp
+++ b/lib/Target/X86/X86ISelSimple.cpp
@@ -1257,7 +1257,7 @@
switch (Align & 3) {
case 2: // WORD aligned
if (ConstantInt *I = dyn_cast<ConstantInt>(CI.getOperand(3))) {
- CountReg = getReg(ConstantUInt::get(Type::UIntTy, I->getRawValue()/2));
+ CountReg =getReg(ConstantUInt::get(Type::UIntTy, I->getRawValue()/2));
} else {
CountReg = makeAnotherReg(Type::IntTy);
BuildMI(BB, X86::SHRir32, 2, CountReg).addReg(ByteReg).addZImm(1);
@@ -1267,7 +1267,7 @@
break;
case 0: // DWORD aligned
if (ConstantInt *I = dyn_cast<ConstantInt>(CI.getOperand(3))) {
- CountReg = getReg(ConstantUInt::get(Type::UIntTy, I->getRawValue()/4));
+ CountReg =getReg(ConstantUInt::get(Type::UIntTy, I->getRawValue()/4));
} else {
CountReg = makeAnotherReg(Type::IntTy);
BuildMI(BB, X86::SHRir32, 2, CountReg).addReg(ByteReg).addZImm(2);