commit 3061c4442ec9d15d0e38d1cf2841e8a21938cf5e
author Jakob Stoklund Olesen <stoklund@2pi.dk> Fri Sep 03 00:35:18 2010 +0000
committer Jakob Stoklund Olesen <stoklund@2pi.dk> Fri Sep 03 00:35:18 2010 +0000
tree dc41e223fa56dafdc695b8d8ced2a945373a1761
parent 7853cd0beaf219630d326358908eb8e1c2baf8db

Don't call Predicate_* from X86 target.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@112921 91177308-0d34-0410-b5e6-96231b3b80d8

lib/Target/X86/X86ISelDAGToDAG.cpp

diff --git a/lib/Target/X86/X86ISelDAGToDAG.cpp b/lib/Target/X86/X86ISelDAGToDAG.cpp
index a3451f5..c523441 100644
--- a/lib/Target/X86/X86ISelDAGToDAG.cpp
+++ b/lib/Target/X86/X86ISelDAGToDAG.cpp
@@ -171,6 +171,17 @@
 
     virtual void PreprocessISelDAG();
 
+    inline bool immSext8(SDNode *N) const {
+      return isInt<8>(cast<ConstantSDNode>(N)->getSExtValue());
+    }
+
+    // i64immSExt32 predicate - True if the 64-bit immediate fits in a 32-bit
+    // sign extended field.
+    inline bool i64immSExt32(SDNode *N) const {
+      uint64_t v = cast<ConstantSDNode>(N)->getZExtValue();
+      return (int64_t)v == (int32_t)v;
+    }
+
 // Include the pieces autogenerated from the target description.
 #include "X86GenDAGISel.inc"
 
@@ -1396,7 +1407,7 @@
       Opc = X86::LOCK_DEC16m;
     else if (isSub) {
       if (isCN) {
-        if (Predicate_immSext8(Val.getNode()))
+        if (immSext8(Val.getNode()))
           Opc = X86::LOCK_SUB16mi8;
         else
           Opc = X86::LOCK_SUB16mi;
@@ -1404,7 +1415,7 @@
         Opc = X86::LOCK_SUB16mr;
     } else {
       if (isCN) {
-        if (Predicate_immSext8(Val.getNode()))
+        if (immSext8(Val.getNode()))
           Opc = X86::LOCK_ADD16mi8;
         else
           Opc = X86::LOCK_ADD16mi;
@@ -1419,7 +1430,7 @@
       Opc = X86::LOCK_DEC32m;
     else if (isSub) {
       if (isCN) {
-        if (Predicate_immSext8(Val.getNode()))
+        if (immSext8(Val.getNode()))
           Opc = X86::LOCK_SUB32mi8;
         else
           Opc = X86::LOCK_SUB32mi;
@@ -1427,7 +1438,7 @@
         Opc = X86::LOCK_SUB32mr;
     } else {
       if (isCN) {
-        if (Predicate_immSext8(Val.getNode()))
+        if (immSext8(Val.getNode()))
           Opc = X86::LOCK_ADD32mi8;
         else
           Opc = X86::LOCK_ADD32mi;
@@ -1443,17 +1454,17 @@
     else if (isSub) {
       Opc = X86::LOCK_SUB64mr;
       if (isCN) {
-        if (Predicate_immSext8(Val.getNode()))
+        if (immSext8(Val.getNode()))
           Opc = X86::LOCK_SUB64mi8;
-        else if (Predicate_i64immSExt32(Val.getNode()))
+        else if (i64immSExt32(Val.getNode()))
           Opc = X86::LOCK_SUB64mi32;
       }
     } else {
       Opc = X86::LOCK_ADD64mr;
       if (isCN) {
-        if (Predicate_immSext8(Val.getNode()))
+        if (immSext8(Val.getNode()))
           Opc = X86::LOCK_ADD64mi8;
-        else if (Predicate_i64immSExt32(Val.getNode()))
+        else if (i64immSExt32(Val.getNode()))
           Opc = X86::LOCK_ADD64mi32;
       }
     }

lib/Target/X86/X86Instr64bit.td

diff --git a/lib/Target/X86/X86Instr64bit.td b/lib/Target/X86/X86Instr64bit.td
index 1f11dc1d..0884b61 100644
--- a/lib/Target/X86/X86Instr64bit.td
+++ b/lib/Target/X86/X86Instr64bit.td
@@ -73,11 +73,7 @@
   return getI32Imm((unsigned)N->getZExtValue());
 }]>;
 
-def i64immSExt32  : PatLeaf<(i64 imm), [{
-  // i64immSExt32 predicate - True if the 64-bit immediate fits in a 32-bit
-  // sign extended field.
-  return (int64_t)N->getZExtValue() == (int32_t)N->getZExtValue();
-}]>;
+def i64immSExt32  : PatLeaf<(i64 imm), [{ return i64immSExt32(N); }]>;
 
 
 def i64immZExt32  : PatLeaf<(i64 imm), [{

lib/Target/X86/X86InstrInfo.td

diff --git a/lib/Target/X86/X86InstrInfo.td b/lib/Target/X86/X86InstrInfo.td
index 84fde71..ae48cee 100644
--- a/lib/Target/X86/X86InstrInfo.td
+++ b/lib/Target/X86/X86InstrInfo.td
@@ -414,9 +414,7 @@
 def X86_COND_P   : PatLeaf<(i8 14)>; // alt. COND_PE
 def X86_COND_S   : PatLeaf<(i8 15)>;
 
-def immSext8 : PatLeaf<(imm), [{
-  return N->getSExtValue() == (int8_t)N->getSExtValue();
-}]>;
+def immSext8 : PatLeaf<(imm), [{ return immSext8(N); }]>;
 
 def i16immSExt8  : PatLeaf<(i16 immSext8)>;
 def i32immSExt8  : PatLeaf<(i32 immSext8)>;