commit 30a343aeedf777f9b8b6be9823da750afbf765b1
author Evan Cheng <evan.cheng@apple.com> Fri Jan 07 21:08:26 2011 +0000
committer Evan Cheng <evan.cheng@apple.com> Fri Jan 07 21:08:26 2011 +0000
tree e6b405c527a518555d2cb424546fa4ddeae4f84f
parent eaff66a8950bb9ed76e830c4ded7e0b695ab6904

DBG_VALUE does not have any side effects; it also makes no sense to mark it cheap as a copy.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@123031 91177308-0d34-0410-b5e6-96231b3b80d8

include/llvm/Target/Target.td

diff --git a/include/llvm/Target/Target.td b/include/llvm/Target/Target.td
index f7a029b..e88a09e 100644
--- a/include/llvm/Target/Target.td
+++ b/include/llvm/Target/Target.td
@@ -484,7 +484,7 @@
   let OutOperandList = (outs);
   let InOperandList = (ins variable_ops);
   let AsmString = "DBG_VALUE";
-  let isAsCheapAsAMove = 1;
+  let neverHasSideEffects = 1;
 }
 def REG_SEQUENCE : Instruction {
   let OutOperandList = (outs unknown:$dst);

lib/CodeGen/MachineInstr.cpp

diff --git a/lib/CodeGen/MachineInstr.cpp b/lib/CodeGen/MachineInstr.cpp
index bc2a545..ccb2ffb 100644
--- a/lib/CodeGen/MachineInstr.cpp
+++ b/lib/CodeGen/MachineInstr.cpp
@@ -1115,7 +1115,9 @@
     SawStore = true;
     return false;
   }
-  if (TID->isTerminator() || TID->hasUnmodeledSideEffects())
+
+  if (isLabel() || isDebugValue() ||
+      TID->isTerminator() || TID->hasUnmodeledSideEffects())
     return false;
 
   // See if this instruction does a load.  If so, we have to guarantee that the

lib/CodeGen/PeepholeOptimizer.cpp

diff --git a/lib/CodeGen/PeepholeOptimizer.cpp b/lib/CodeGen/PeepholeOptimizer.cpp
index 07c2b80..1ddfe8b 100644
--- a/lib/CodeGen/PeepholeOptimizer.cpp
+++ b/lib/CodeGen/PeepholeOptimizer.cpp
@@ -336,7 +336,9 @@
       MachineInstr *MI = &*MII++;
       LocalMIs.insert(MI);
 
-      if (MI->getDesc().hasUnmodeledSideEffects())
+      if (MI->isLabel() || MI->isPHI() || MI->isImplicitDef() ||
+          MI->isKill() || MI->isInlineAsm() || MI->isDebugValue() ||
+          MI->getDesc().hasUnmodeledSideEffects())
         continue;
 
       if (MI->getDesc().isCompare()) {

lib/CodeGen/VirtRegRewriter.cpp

diff --git a/lib/CodeGen/VirtRegRewriter.cpp b/lib/CodeGen/VirtRegRewriter.cpp
index 14ee69d..d04b928 100644
--- a/lib/CodeGen/VirtRegRewriter.cpp
+++ b/lib/CodeGen/VirtRegRewriter.cpp
@@ -1620,7 +1620,8 @@
   const TargetInstrDesc &TID = MI.getDesc();
   if (TID.mayLoad() || TID.mayStore() || TID.isCall() || TID.isTerminator() ||
       TID.isCall() || TID.isBarrier() || TID.isReturn() ||
-      TID.hasUnmodeledSideEffects())
+      TID.hasUnmodeledSideEffects() ||
+      MI.isLabel() || MI.isDebugValue())
     return false;
   for (unsigned i = 0, e = MI.getNumOperands(); i != e; ++i) {
     MachineOperand &MO = MI.getOperand(i);