commit 3116dce33840a115130c5f8ffcb9679d023496d6
author Bill Wendling <isanbard@gmail.com> Mon Mar 07 23:38:41 2011 +0000
committer Bill Wendling <isanbard@gmail.com> Mon Mar 07 23:38:41 2011 +0000
tree 5785ba082080308e283bebd9de4006abfd756360
parent 0d8ccaa5c8db820b5b93f37e51563148c57ba6b8

Rename the narrow shift right immediate operands to "shr_imm*" operands. Also
expand the testing of the narrowing shift right instructions.

No functionality change.


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@127193 91177308-0d34-0410-b5e6-96231b3b80d8

lib/Target/ARM/ARMMCCodeEmitter.cpp

diff --git a/lib/Target/ARM/ARMMCCodeEmitter.cpp b/lib/Target/ARM/ARMMCCodeEmitter.cpp
index 48884a1..10607b1 100644
--- a/lib/Target/ARM/ARMMCCodeEmitter.cpp
+++ b/lib/Target/ARM/ARMMCCodeEmitter.cpp
@@ -278,12 +278,14 @@
   unsigned getAddrMode6OffsetOpValue(const MCInst &MI, unsigned Op,
                                      SmallVectorImpl<MCFixup> &Fixups) const;
 
-  unsigned getNarrowShiftRight16Imm(const MCInst &MI, unsigned Op,
-                                    SmallVectorImpl<MCFixup> &Fixups) const;
-  unsigned getNarrowShiftRight32Imm(const MCInst &MI, unsigned Op,
-                                    SmallVectorImpl<MCFixup> &Fixups) const;
-  unsigned getNarrowShiftRight64Imm(const MCInst &MI, unsigned Op,
-                                    SmallVectorImpl<MCFixup> &Fixups) const;
+  unsigned getShiftRight8Imm(const MCInst &MI, unsigned Op,
+                             SmallVectorImpl<MCFixup> &Fixups) const;
+  unsigned getShiftRight16Imm(const MCInst &MI, unsigned Op,
+                              SmallVectorImpl<MCFixup> &Fixups) const;
+  unsigned getShiftRight32Imm(const MCInst &MI, unsigned Op,
+                              SmallVectorImpl<MCFixup> &Fixups) const;
+  unsigned getShiftRight64Imm(const MCInst &MI, unsigned Op,
+                              SmallVectorImpl<MCFixup> &Fixups) const;
 
   unsigned NEONThumb2DataIPostEncoder(const MCInst &MI,
                                       unsigned EncodedValue) const;
@@ -1209,23 +1211,29 @@
 }
 
 unsigned ARMMCCodeEmitter::
-getNarrowShiftRight16Imm(const MCInst &MI, unsigned Op,
-                         SmallVectorImpl<MCFixup> &Fixups) const {
+getShiftRight8Imm(const MCInst &MI, unsigned Op,
+                  SmallVectorImpl<MCFixup> &Fixups) const {
   return 8 - MI.getOperand(Op).getImm();
 }
 
 unsigned ARMMCCodeEmitter::
-getNarrowShiftRight32Imm(const MCInst &MI, unsigned Op,
-                         SmallVectorImpl<MCFixup> &Fixups) const {
+getShiftRight16Imm(const MCInst &MI, unsigned Op,
+                   SmallVectorImpl<MCFixup> &Fixups) const {
   return 16 - MI.getOperand(Op).getImm();
 }
 
 unsigned ARMMCCodeEmitter::
-getNarrowShiftRight64Imm(const MCInst &MI, unsigned Op,
-                         SmallVectorImpl<MCFixup> &Fixups) const {
+getShiftRight32Imm(const MCInst &MI, unsigned Op,
+                   SmallVectorImpl<MCFixup> &Fixups) const {
   return 32 - MI.getOperand(Op).getImm();
 }
 
+unsigned ARMMCCodeEmitter::
+getShiftRight64Imm(const MCInst &MI, unsigned Op,
+                   SmallVectorImpl<MCFixup> &Fixups) const {
+  return 64 - MI.getOperand(Op).getImm();
+}
+
 void ARMMCCodeEmitter::
 EncodeInstruction(const MCInst &MI, raw_ostream &OS,
                   SmallVectorImpl<MCFixup> &Fixups) const {