commit 31559081a4285f4b7282e765aea4ec8a8e1d396c
author Andrew Lenharth <andrewl@lenharth.org> Thu Jun 30 19:32:57 2005 +0000
committer Andrew Lenharth <andrewl@lenharth.org> Thu Jun 30 19:32:57 2005 +0000
tree 6baa62114fdc839cb00bc682f1daacf0dba5dcf1
parent 9d416f713e8b9e4f0c0c2b3f6f57ce2dd8993209

oops


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@22320 91177308-0d34-0410-b5e6-96231b3b80d8

lib/CodeGen/SelectionDAG/LegalizeDAG.cpp

diff --git a/lib/CodeGen/SelectionDAG/LegalizeDAG.cpp b/lib/CodeGen/SelectionDAG/LegalizeDAG.cpp
index bf97fea..9a27404 100644
--- a/lib/CodeGen/SelectionDAG/LegalizeDAG.cpp
+++ b/lib/CodeGen/SelectionDAG/LegalizeDAG.cpp
@@ -525,8 +525,7 @@
       //f64 = EXTLOAD f32 should expand to LOAD, FP_EXTEND
       if (SrcVT == MVT::f32 && Node->getValueType(0) == MVT::f64) {
         SDOperand Load = DAG.getLoad(SrcVT, Tmp1, Tmp2, Node->getOperand(2));
-        Result = 
-          DAG.getNode(ISD::FP_EXTEND, Node->getValueType(0), Load, SrcVT);
+        Result = DAG.getNode(ISD::FP_EXTEND, Node->getValueType(0), Load);
         if (Op.ResNo)
           return Load.getValue(1);
         return Result;