Turn few asserts into errors / unreachable's
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@76313 91177308-0d34-0410-b5e6-96231b3b80d8
diff --git a/lib/Target/SystemZ/AsmPrinter/SystemZAsmPrinter.cpp b/lib/Target/SystemZ/AsmPrinter/SystemZAsmPrinter.cpp
index 24f4114..07c8ed0 100644
--- a/lib/Target/SystemZ/AsmPrinter/SystemZAsmPrinter.cpp
+++ b/lib/Target/SystemZ/AsmPrinter/SystemZAsmPrinter.cpp
@@ -183,7 +183,7 @@
if (printInstruction(MI))
return;
- assert(0 && "Should not happen");
+ llvm_unreachable("Unreachable!");
}
void SystemZAsmPrinter::printPCRelImmOperand(const MachineInstr *MI, int OpNum) {
@@ -282,7 +282,7 @@
switch (MO.getTargetFlags()) {
default:
- assert(0 && "Unknown target flag on GV operand");
+ llvm_unreachable("Unknown target flag on GV operand");
case SystemZII::MO_NO_FLAG:
break;
case SystemZII::MO_GOTENT: O << "@GOTENT"; break;
diff --git a/lib/Target/SystemZ/SystemZISelLowering.cpp b/lib/Target/SystemZ/SystemZISelLowering.cpp
index b1d42cb..10e969d 100644
--- a/lib/Target/SystemZ/SystemZISelLowering.cpp
+++ b/lib/Target/SystemZ/SystemZISelLowering.cpp
@@ -161,7 +161,7 @@
case ISD::JumpTable: return LowerJumpTable(Op, DAG);
case ISD::ConstantPool: return LowerConstantPool(Op, DAG);
default:
- assert(0 && "unimplemented operand");
+ llvm_unreachable("Should not custom lower this!");
return SDValue();
}
}
@@ -177,7 +177,7 @@
unsigned CC = cast<ConstantSDNode>(Op.getOperand(1))->getZExtValue();
switch (CC) {
default:
- assert(0 && "Unsupported calling convention");
+ llvm_unreachable("Unsupported calling convention");
case CallingConv::C:
case CallingConv::Fast:
return LowerCCCArguments(Op, DAG);
@@ -189,7 +189,7 @@
unsigned CallingConv = TheCall->getCallingConv();
switch (CallingConv) {
default:
- assert(0 && "Unsupported calling convention");
+ llvm_unreachable("Unsupported calling convention");
case CallingConv::Fast:
case CallingConv::C:
return LowerCCCCallTo(Op, DAG, CallingConv);
@@ -215,7 +215,8 @@
CCState CCInfo(CC, isVarArg, getTargetMachine(), ArgLocs, DAG.getContext());
CCInfo.AnalyzeFormalArguments(Op.getNode(), CC_SystemZ);
- assert(!isVarArg && "Varargs not supported yet");
+ if (isVarArg)
+ llvm_report_error("Varargs not supported yet");
SmallVector<SDValue, 16> ArgValues;
for (unsigned i = 0, e = ArgLocs.size(); i != e; ++i) {
@@ -534,7 +535,8 @@
bool isUnsigned = false;
SystemZCC::CondCodes TCC;
switch (CC) {
- default: assert(0 && "Invalid integer condition!");
+ default:
+ llvm_unreachable("Invalid integer condition!");
case ISD::SETEQ:
case ISD::SETOEQ:
TCC = SystemZCC::E;
diff --git a/lib/Target/SystemZ/SystemZInstrInfo.cpp b/lib/Target/SystemZ/SystemZInstrInfo.cpp
index 27bd47d..b7dfab5 100644
--- a/lib/Target/SystemZ/SystemZInstrInfo.cpp
+++ b/lib/Target/SystemZ/SystemZInstrInfo.cpp
@@ -81,7 +81,7 @@
} else if (RC == &SystemZ::GR128RegClass) {
Opc = SystemZ::MOV128mr;
} else
- assert(0 && "Unsupported regclass to store");
+ llvm_unreachable("Unsupported regclass to store");
addFrameReference(BuildMI(MBB, MI, DL, get(Opc)), FrameIdx)
.addReg(SrcReg, getKillRegState(isKill));
@@ -110,7 +110,7 @@
} else if (RC == &SystemZ::GR128RegClass) {
Opc = SystemZ::MOV128rm;
} else
- assert(0 && "Unsupported regclass to load");
+ llvm_unreachable("Unsupported regclass to load");
addFrameReference(BuildMI(MBB, MI, DL, get(Opc), DestReg), FrameIdx);
}
@@ -584,7 +584,7 @@
SystemZInstrInfo::getBrCond(SystemZCC::CondCodes CC) const {
switch (CC) {
default:
- assert(0 && "Unknown condition code!");
+ llvm_unreachable("Unknown condition code!");
case SystemZCC::O: return get(SystemZ::JO);
case SystemZCC::H: return get(SystemZ::JH);
case SystemZCC::NLE: return get(SystemZ::JNLE);
@@ -627,7 +627,7 @@
SystemZInstrInfo::getOppositeCondition(SystemZCC::CondCodes CC) const {
switch (CC) {
default:
- assert(0 && "Invalid condition!");
+ llvm_unreachable("Invalid condition!");
case SystemZCC::O: return SystemZCC::NO;
case SystemZCC::H: return SystemZCC::NH;
case SystemZCC::NLE: return SystemZCC::LE;
@@ -649,7 +649,7 @@
SystemZInstrInfo::getLongDispOpc(unsigned Opc) const {
switch (Opc) {
default:
- assert(0 && "Don't have long disp version of this instruction");
+ llvm_unreachable("Don't have long disp version of this instruction");
case SystemZ::MOV32mr: return get(SystemZ::MOV32mry);
case SystemZ::MOV32rm: return get(SystemZ::MOV32rmy);
case SystemZ::MOVSX32rm16: return get(SystemZ::MOVSX32rm16y);