Encode the conditional execution predicate when JITing.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@57258 91177308-0d34-0410-b5e6-96231b3b80d8
diff --git a/lib/Target/ARM/ARMCodeEmitter.cpp b/lib/Target/ARM/ARMCodeEmitter.cpp
index 13f7903..574c14e 100644
--- a/lib/Target/ARM/ARMCodeEmitter.cpp
+++ b/lib/Target/ARM/ARMCodeEmitter.cpp
@@ -256,8 +256,8 @@
unsigned ARMCodeEmitter::getAddrModeNoneInstrBinary(const MachineInstr &MI,
const TargetInstrDesc &TID,
unsigned Binary) {
- // FIXME: Assume CC is AL for now.
- Binary |= ARMCC::AL << 28;
+ // Set the conditional execution predicate
+ Binary |= II->getPredicate(&MI) << 28;
switch (TID.TSFlags & ARMII::FormMask) {
default:
@@ -376,8 +376,8 @@
unsigned ARMCodeEmitter::getAddrMode1InstrBinary(const MachineInstr &MI,
const TargetInstrDesc &TID,
unsigned Binary) {
- // FIXME: Assume CC is AL for now.
- Binary |= ARMCC::AL << 28;
+ // Set the conditional execution predicate
+ Binary |= II->getPredicate(&MI) << 28;
// Encode S bit if MI modifies CPSR.
Binary |= getAddrMode1SBit(MI, TID);
@@ -429,8 +429,8 @@
unsigned ARMCodeEmitter::getAddrMode2InstrBinary(const MachineInstr &MI,
const TargetInstrDesc &TID,
unsigned Binary) {
- // FIXME: Assume CC is AL for now.
- Binary |= ARMCC::AL << 28;
+ // Set the conditional execution predicate
+ Binary |= II->getPredicate(&MI) << 28;
// Set first operand
Binary |= getMachineOpValue(MI, 0) << ARMII::RegRdShift;
@@ -470,8 +470,8 @@
unsigned ARMCodeEmitter::getAddrMode3InstrBinary(const MachineInstr &MI,
const TargetInstrDesc &TID,
unsigned Binary) {
- // FIXME: Assume CC is AL for now.
- Binary |= ARMCC::AL << 28;
+ // Set the conditional execution predicate
+ Binary |= II->getPredicate(&MI) << 28;
// Set first operand
Binary |= getMachineOpValue(MI, 0) << ARMII::RegRdShift;
@@ -507,8 +507,8 @@
unsigned ARMCodeEmitter::getAddrMode4InstrBinary(const MachineInstr &MI,
const TargetInstrDesc &TID,
unsigned Binary) {
- // FIXME: Assume CC is AL for now.
- Binary |= ARMCC::AL << 28;
+ // Set the conditional execution predicate
+ Binary |= II->getPredicate(&MI) << 28;
// Set first operand
Binary |= getMachineOpValue(MI, 0) << ARMII::RegRnShift;