Fix a tblgen problem handling variable_ops in tblgen instruction
definitions. This adds a new construct, "discard", for indicating
that a named node in the input matching pattern is to be discarded,
instead of corresponding to a node in the output pattern. This
allows tblgen to know where the arguments for the varaible_ops are
supposed to begin.
This fixes "rdar://5791600", whatever that is ;-).
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@51699 91177308-0d34-0410-b5e6-96231b3b80d8
diff --git a/lib/Target/Target.td b/lib/Target/Target.td
index a268e16..92c4057 100644
--- a/lib/Target/Target.td
+++ b/lib/Target/Target.td
@@ -259,6 +259,12 @@
/// of operands.
def variable_ops;
+/// discard definition - Mark this operand as being matched in the input
+/// but omitted from the output. This is necessary in some situations
+/// involving variable_ops to help the pattern matcher determine which
+/// input nodes to forward on to the variable_ops portion of the output.
+def discard;
+
/// ptr_rc definition - Mark this operand as being a pointer value whose
/// register class is resolved dynamically via a callback to TargetInstrInfo.
/// FIXME: We should probably change this to a class which contain a list of
diff --git a/lib/Target/TargetSelectionDAG.td b/lib/Target/TargetSelectionDAG.td
index f194443..9def220 100644
--- a/lib/Target/TargetSelectionDAG.td
+++ b/lib/Target/TargetSelectionDAG.td
@@ -470,6 +470,7 @@
def vtInt : PatLeaf<(vt), [{ return MVT::isInteger(N->getVT()); }]>;
def vtFP : PatLeaf<(vt), [{ return MVT::isFloatingPoint(N->getVT()); }]>;
+def immAllZeros : PatLeaf<(imm), [{ return N->isNullValue(); }]>;
def immAllOnes : PatLeaf<(imm), [{ return N->isAllOnesValue(); }]>;
def immAllOnesV: PatLeaf<(build_vector), [{
return ISD::isBuildVectorAllOnes(N);
diff --git a/lib/Target/X86/X86ISelDAGToDAG.cpp b/lib/Target/X86/X86ISelDAGToDAG.cpp
index 576661d..bb8c58a 100644
--- a/lib/Target/X86/X86ISelDAGToDAG.cpp
+++ b/lib/Target/X86/X86ISelDAGToDAG.cpp
@@ -1175,35 +1175,6 @@
case X86ISD::GlobalBaseReg:
return getGlobalBaseReg();
- // FIXME: This is a workaround for a tblgen problem: rdar://5791600
- case X86ISD::RET_FLAG:
- if (ConstantSDNode *Amt = dyn_cast<ConstantSDNode>(N.getOperand(1))) {
- if (Amt->getSignExtended() != 0) break;
-
- // Match (X86retflag 0).
- SDOperand Chain = N.getOperand(0);
- bool HasInFlag = N.getOperand(N.getNumOperands()-1).getValueType()
- == MVT::Flag;
- SmallVector<SDOperand, 8> Ops0;
- AddToISelQueue(Chain);
- SDOperand InFlag(0, 0);
- if (HasInFlag) {
- InFlag = N.getOperand(N.getNumOperands()-1);
- AddToISelQueue(InFlag);
- }
- for (unsigned i = 2, e = N.getNumOperands()-(HasInFlag?1:0); i != e;
- ++i) {
- AddToISelQueue(N.getOperand(i));
- Ops0.push_back(N.getOperand(i));
- }
- Ops0.push_back(Chain);
- if (HasInFlag)
- Ops0.push_back(InFlag);
- return CurDAG->getTargetNode(X86::RET, MVT::Other,
- &Ops0[0], Ops0.size());
- }
- break;
-
case ISD::ADD: {
// Turn ADD X, c to MOV32ri X+c. This cannot be done with tblgen'd
// code and is matched first so to prevent it from being turned into
diff --git a/lib/Target/X86/X86InstrInfo.td b/lib/Target/X86/X86InstrInfo.td
index 843fbd0..d0bd955 100644
--- a/lib/Target/X86/X86InstrInfo.td
+++ b/lib/Target/X86/X86InstrInfo.td
@@ -45,7 +45,7 @@
def SDT_X86CallSeqEnd : SDCallSeqEnd<[ SDTCisVT<0, i32>,
SDTCisVT<1, i32> ]>;
-def SDT_X86Call : SDTypeProfile<0, 1, [SDTCisVT<0, iPTR>]>;
+def SDT_X86Call : SDTypeProfile<0, -1, [SDTCisVT<0, iPTR>]>;
def SDTX86RepStr : SDTypeProfile<0, 1, [SDTCisVT<0, OtherVT>]>;
@@ -322,9 +322,9 @@
// Return instructions.
let isTerminator = 1, isReturn = 1, isBarrier = 1,
hasCtrlDep = 1, FPForm = SpecialFP, FPFormBits = SpecialFP.Value in {
- def RET : I <0xC3, RawFrm, (outs), (ins variable_ops),
+ def RET : I <0xC3, RawFrm, (outs), (ins discard:$amt, variable_ops),
"ret",
- [/*(X86retflag 0)*/ /*FIXME: Disabled: rdar://5791600*/]>;
+ [(X86retflag immAllZeros:$amt)]>;
def RETI : Ii16<0xC2, RawFrm, (outs), (ins i16imm:$amt, variable_ops),
"ret\t$amt",
[(X86retflag imm:$amt)]>;