Remove the Alpha backend.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@143164 91177308-0d34-0410-b5e6-96231b3b80d8
diff --git a/docs/CMake.html b/docs/CMake.html
index ac07b0d..90ead41 100644
--- a/docs/CMake.html
+++ b/docs/CMake.html
@@ -249,7 +249,7 @@
<dd>Semicolon-separated list of targets to build, or <i>all</i> for
building all targets. Case-sensitive. For Visual C++ defaults
to <i>X86</i>. On the other cases defaults to <i>all</i>. Example:
- <i>-DLLVM_TARGETS_TO_BUILD="X86;PowerPC;Alpha"</i>.</dd>
+ <i>-DLLVM_TARGETS_TO_BUILD="X86;PowerPC"</i>.</dd>
<dt><b>LLVM_BUILD_TOOLS</b>:BOOL</dt>
<dd>Build LLVM tools. Defaults to ON. Targets for building each tool
diff --git a/docs/CodeGenerator.html b/docs/CodeGenerator.html
index 8bb680c..15344da 100644
--- a/docs/CodeGenerator.html
+++ b/docs/CodeGenerator.html
@@ -2208,7 +2208,6 @@
<tr>
<th>Feature</th>
<th>ARM</th>
- <th>Alpha</th>
<th>CellSPU</th>
<th>MBlaze</th>
<th>MSP430</th>
@@ -2223,7 +2222,6 @@
<tr>
<td><a href="#feat_reliable">is generally reliable</a></td>
<td class="yes"></td> <!-- ARM -->
- <td class="unknown"></td> <!-- Alpha -->
<td class="no"></td> <!-- CellSPU -->
<td class="no"></td> <!-- MBlaze -->
<td class="unknown"></td> <!-- MSP430 -->
@@ -2238,7 +2236,6 @@
<tr>
<td><a href="#feat_asmparser">assembly parser</a></td>
<td class="no"></td> <!-- ARM -->
- <td class="no"></td> <!-- Alpha -->
<td class="no"></td> <!-- CellSPU -->
<td class="yes"></td> <!-- MBlaze -->
<td class="no"></td> <!-- MSP430 -->
@@ -2253,7 +2250,6 @@
<tr>
<td><a href="#feat_disassembler">disassembler</a></td>
<td class="yes"></td> <!-- ARM -->
- <td class="no"></td> <!-- Alpha -->
<td class="no"></td> <!-- CellSPU -->
<td class="yes"></td> <!-- MBlaze -->
<td class="no"></td> <!-- MSP430 -->
@@ -2268,7 +2264,6 @@
<tr>
<td><a href="#feat_inlineasm">inline asm</a></td>
<td class="yes"></td> <!-- ARM -->
- <td class="unknown"></td> <!-- Alpha -->
<td class="no"></td> <!-- CellSPU -->
<td class="yes"></td> <!-- MBlaze -->
<td class="unknown"></td> <!-- MSP430 -->
@@ -2283,7 +2278,6 @@
<tr>
<td><a href="#feat_jit">jit</a></td>
<td class="partial"><a href="#feat_jit_arm">*</a></td> <!-- ARM -->
- <td class="no"></td> <!-- Alpha -->
<td class="no"></td> <!-- CellSPU -->
<td class="no"></td> <!-- MBlaze -->
<td class="unknown"></td> <!-- MSP430 -->
@@ -2298,7 +2292,6 @@
<tr>
<td><a href="#feat_objectwrite">.o file writing</a></td>
<td class="no"></td> <!-- ARM -->
- <td class="no"></td> <!-- Alpha -->
<td class="no"></td> <!-- CellSPU -->
<td class="yes"></td> <!-- MBlaze -->
<td class="no"></td> <!-- MSP430 -->
@@ -2313,7 +2306,6 @@
<tr>
<td><a href="#feat_tailcall">tail calls</a></td>
<td class="yes"></td> <!-- ARM -->
- <td class="unknown"></td> <!-- Alpha -->
<td class="no"></td> <!-- CellSPU -->
<td class="no"></td> <!-- MBlaze -->
<td class="unknown"></td> <!-- MSP430 -->
diff --git a/docs/CompilerWriterInfo.html b/docs/CompilerWriterInfo.html
index d9201fc..857a1d4 100644
--- a/docs/CompilerWriterInfo.html
+++ b/docs/CompilerWriterInfo.html
@@ -21,7 +21,6 @@
<ol>
<li><a href="#hw">Hardware</a>
<ol>
- <li><a href="#alpha">Alpha</a></li>
<li><a href="#arm">ARM</a></li>
<li><a href="#ia64">Itanium</a></li>
<li><a href="#mips">MIPS</a></li>
@@ -49,17 +48,6 @@
<div>
<!-- ======================================================================= -->
-<h3><a name="alpha">Alpha</a></h3>
-
-<div>
-<ul>
-<li><a
-href="http://ftp.digital.com/pub/Digital/info/semiconductor/literature/dsc-library.html">Alpha manuals</a>
-</li>
-</ul>
-</div>
-
-<!-- ======================================================================= -->
<h3><a name="arm">ARM</a></h3>
<div>
diff --git a/docs/UsingLibraries.html b/docs/UsingLibraries.html
index 2973452..0c58e54 100644
--- a/docs/UsingLibraries.html
+++ b/docs/UsingLibraries.html
@@ -126,8 +126,6 @@
<td>Aggressive instruction selector for directed acyclic graphs</td></tr>
<tr><th colspan="3">Target Libraries</th></tr>
- <tr><td>LLVMAlpha</td><td><tt>.o</tt></td>
- <td>Code generation for Alpha architecture</td></tr>
<tr><td>LLVMARM</td><td><tt>.o</tt></td>
<td>Code generation for ARM architecture</td></tr>
<tr><td>LLVMCBackend</td><td><tt>.o</tt></td>
@@ -333,14 +331,6 @@
<li>libLLVMSystem.a</li>
<li>libLLVMTarget.a</li>
</ul></dd>
- <dt><b>LLVMAlpha.o</b></dt><dd><ul>
- <li>libLLVMCodeGen.a</li>
- <li>libLLVMCore.a</li>
- <li>libLLVMSelectionDAG.a</li>
- <li>libLLVMSupport.a</li>
- <li>libLLVMSystem.a</li>
- <li>libLLVMTarget.a</li>
- </ul></dd>
<dt><b>LLVMCBackend.o</b></dt><dd><ul>
<li>libLLVMAnalysis.a</li>
<li>libLLVMCodeGen.a</li>