commit 33d73eb2bc94ca1dcc02c1afbd56200d46560310
author Scott Michel <scottm@aero.org> Fri Nov 21 02:56:16 2008 +0000
committer Scott Michel <scottm@aero.org> Fri Nov 21 02:56:16 2008 +0000
tree a409a4b30f14b1dd7a3abd0cc7fe4b9590dd6826
parent 9560f98ded31ac238ed1b77d50a58da51bec1543

CellSPU:
(a) Fix bgs 3052, 3057
(b) Incorporate Duncan's suggestions re: i1 promotion
(c) Indentation updates.


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@59790 91177308-0d34-0410-b5e6-96231b3b80d8

lib/Target/CellSPU/SPUInstrInfo.cpp

diff --git a/lib/Target/CellSPU/SPUInstrInfo.cpp b/lib/Target/CellSPU/SPUInstrInfo.cpp
index d10f2b8..510b050 100644
--- a/lib/Target/CellSPU/SPUInstrInfo.cpp
+++ b/lib/Target/CellSPU/SPUInstrInfo.cpp
@@ -161,7 +161,7 @@
   case SPU::STQDr64:
   case SPU::STQDr32:
   case SPU::STQDr16:
-    // case SPU::STQDr8:
+  case SPU::STQDr8:
   case SPU::STQXv16i8:
   case SPU::STQXv8i16:
   case SPU::STQXv4i32:
@@ -171,7 +171,7 @@
   case SPU::STQXr64:
   case SPU::STQXr32:
   case SPU::STQXr16:
-    // case SPU::STQXr8:
+  case SPU::STQXr8:
     if (MI->getOperand(1).isImm() && !MI->getOperand(1).getImm() &&
         MI->getOperand(2).isFI()) {
       FrameIndex = MI->getOperand(2).getIndex();